Chaochao Feng

According to our database1, Chaochao Feng authored at least 20 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
LOSSS-Logic Synthesis based on Several Stateful logic gates for high time-efficient computing.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2021
Stage-based Path Delay Prediction with Customized Machine Learning Technique.
Proceedings of the EITCE 2021: 5th International Conference on Electronic Information Technology and Computer Engineering, Xiamen, China, October 22, 2021

2020
A Machine Learning Framework with Feature Selection for Floorplan Acceleration in IC Physical Design.
J. Comput. Sci. Technol., 2020

2018
A Low-Overhead Multicast Bufferless Router with Reconfigurable Banyan Network.
Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

A parameterized timing-aware flip-flop merging algorithm for clock power reduction.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Mobile relay deployment in multihop relay networks.
Comput. Commun., 2017

2016
Thermal optimal task allocation algorithm for multi-core 3D IC with interlayer cooling system.
IEICE Electron. Express, 2016

2015
Exploring partitioning methods for multicast in 3D bufferless Network on Chip.
IEICE Electron. Express, 2015

Partitioning Methods for Multicast in Bufferless 3D Network on Chip.
Proceedings of the Computer Engineering and Technology - 19th CCF Conference, 2015

Performance analysis of on-chip bufferless router with multi-ejection ports.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
Mobile relay deployment based on Markov chains in WiMAX networks.
Proceedings of the IEEE Global Communications Conference, 2014

2013
Addressing Transient and Permanent Faults in NoC With Efficient Fault-Tolerant Deflection Router.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Architecture and Implementation of a Reduced EPIC Processor.
IEICE Trans. Inf. Syst., 2013

Methods for fault tolerance in networks-on-chip.
ACM Comput. Surv., 2013

2012
Support Efficient and Fault-Tolerant Multicast in Bufferless Network-on-Chip.
IEICE Trans. Inf. Syst., 2012

A 1-Cycle 1.25 GHz Bufferless Router for 3D Network-on-Chip.
IEICE Trans. Inf. Syst., 2012

2011
A Low-Overhead Fault-Aware Deflection Routing Algorithm for 3D Network-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Evaluation of deflection routing on various NoC topologies.
Proceedings of the 2011 IEEE 9th International Conference on ASIC, 2011

2010
FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip.
Proceedings of the Third International Workshop on Network on Chip Architectures, 2010


  Loading...