Chao-Yang Yeh

According to our database, Chao-Yang Yeh authored at least 9 papers between 2003 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2022

A 5nm 3.4GHz Tri-Gear ARMv9 CPU Subsystem in a Fully Integrated 5G Flagship Mobile SoC.

Ashish Nayak, HsinChen Chen, Hugh Mair, Rolf Lagerquist, Tao Chen, Anand Rajagopalan, Gordon Gammie, Ramu Madhavaram, Madhur Jagota, C. J. Chung, Jenny Wiedemeier, Bala Meera, Chao-Yang Yeh, Maverick Lin, Curtis Lin, Vincent Lin, Jiun Lin, Y. S. Chen, Barry Chen, Cheng-Yuh Wu, Ryan ChangChien, Ray Tzeng, Kelvin Yang, Achuta Thippana, Ericbill Wang, Shih-Arn Hwang

Proceedings of the IEEE International Solid-State Circuits Conference, 2022

2007

Timing-Aware Power-Noise Reduction in Placement.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

2006

Clock Distribution Architectures: A Comparative Study.

Chao-Yang Yeh, Gustavo R. Wilke, Hongyu Chen, Subodh M. Reddy, Hoa-van Nguyen, Takashi Miyoshi, William W. Walker, Rajeev Murgai

Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005

Timing-aware power noise reduction in layout.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

A sliding window scheme for accurate clock mesh analysis.

Hongyu Chen, Chao-Yang Yeh, Gustavo R. Wilke, Subodh M. Reddy, Hoa-van Nguyen, William W. Walker, Rajeev Murgai

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Skew-programmable clock design for FPGA and skew-aware placement.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

2004

Sequential delay budgeting with interconnect prediction.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

IEEE Trans. Very Large Scale Integr. Syst., 2004

2003

Minimum-Area Sequential Budgeting for FPGA.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Delay budgeting in sequential circuit with application on FPGA placement.

Chao-Yang Yeh, Malgorzata Marek-Sadowska

Proceedings of the 40th Design Automation Conference, 2003