Chao-Wen Tzeng

According to our database¹, Chao-Wen Tzeng authored at least 19 papers between 2007 and 2015.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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On csauthors.net:

Bibliography

2015

Case study of process and design performance debugging with Digital Speed Sensor.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design, Automation and Test, 2015

2014

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Shi-Yu Huang

Pei-Ying Chao

IEEE Trans. Very Large Scale Integr. Syst., 2014

2013

AC-Plus Scan Methodology for Small Delay Testing and Characterization.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Cell-Based Process Resilient Multiphase Clock Generation.

[BibT_eX]

[DOI]

Ruo-Ting Ding

Shi-Yu Huang

Chao-Wen Tzeng

IEEE Trans. Very Large Scale Integr. Syst., 2013

Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

Die-to-Die Clock Synchronization for 3-D IC Using Dual Locking Mechanism.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2013

Case study of yield learning through in-house flow of volume diagnosis.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2012

Cyclic-MPCG: Process-resilient and super-resolution multi-phase clock generation by exploiting the cyclic property.

[BibT_eX]

[DOI]

Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

2011

A fully cell-based design for timing measurement of memory.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2011

2010

Split-Masking: An Output Masking Scheme for Effective Compound Defect Diagnosis in Scan Architecture With Test Compression.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Shi-Yu Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

AF-Test: Adaptive-Frequency Scan Test Methodology for Small-Delay Defects.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009

QC-Fill: Quick-and-Cool X-Filling for Multicasting-Based Scan Test.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Shi-Yu Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Layout-Based Defect-Driven Diagnosis for Intracell Bridging Defects.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Han-Chia Cheng

Shi-Yu Huang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

QC-Fill: An X-Fill method for quick-and-cool scan test.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Shi-Yu Huang

Proceedings of the Design, Automation and Test in Europe, 2009

2008

A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Jheng-Syun Yang

Shi-Yu Huang

ACM Trans. Design Autom. Electr. Syst., 2008

UMC-Scan Test Methodology: Exploiting the Maximum Freedom of Multicasting.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Shi-Yu Huang

IEEE Des. Test Comput., 2008

Two-Gear Low-Power Scan Test.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Shi-Yu Huang

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Diagnosis by Image Recovery: Finding Mixed Multiple Timing Faults in a Scan Chain.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

Shi-Yu Huang

IEEE Trans. Circuits Syst. II Express Briefs, 2007

Robust paradigm for diagnosing hold-time faults in scan chains.

[BibT_eX]

[DOI]

Chao-Wen Tzeng

J.-J. Hsu

Shi-Yu Huang

IET Comput. Digit. Tech., 2007

Chao-Wen Tzeng

Timeline

Legend:

Links

On csauthors.net:

Bibliography

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