Chao Wang

According to our database, Chao Wang authored at least 8 papers between 2006 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2020

Towards an automated design flow for memristor based VLSI circuits.

Lei Xie, Hao Cai, Chao Wang, Jun Yang

Integr., 2020

2017

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach.

Chao Wang, Peng Cao, Bo Liu, Jun Yang

IEICE Electron. Express, 2017

Efficient AES cipher on coarse-grained reconfigurable architecture.

Chao Wang, Peng Cao, Jun Yang

IEICE Electron. Express, 2017

2010

Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme.

Peng Cao, Chao Wang, Longxing Shi

J. Signal Process. Syst., 2010

2009

Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm.

Peng Cao, Chao Wang, Longxing Shi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer.

Peng Cao, Chao Wang, Jun Yang, Longxing Shi

Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

2007

An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform.

Chao Wang, Wu Zhilin, Peng Cao, Li Jie

Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

2006

Energy-optimal dynamic voltage scaling for sporadic tasks.

Bu Aiguo, Longxing Shi, Hu Chen, Li Jie, Chao Wang

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006