Chao-Hsin Lu

According to our database, Chao-Hsin Lu authored at least 6 papers between 2002 and 2021.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2021

An 80MHz-BW 640MS/s Time-Interleaved Passive Noise- Shaping SAR ADC in 22nm FDSOI Process.

Chin-Yu Lin, Ying-Zu Lin, Chih-Hou Tsai, Chao-Hsin Lu

Proceedings of the IEEE International Solid-State Circuits Conference, 2021

2019

A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET.

Ying-Zu Lin, Chin-Yu Lin, Shan-Chih Tsou, Chih-Hou Tsai, Chao-Hsin Lu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2016

A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with fast reference charge neutralization and background timing-skew calibration in 16-nm CMOS.

Ying-Zu Lin, Chih-Hou Tsai, Shan-Chih Tsou, Chao-Hsin Lu

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2012

A 4-in-1 (WiFi/BT/FM/GPS) connectivity SoC with enhanced co-existence performance in 65nm CMOS.

Yuan-Hung Chung, Min Chen, Wei-Kai Hong, Jie-Wei Lai, Sheng-Jau Wong, Chien-Wei Kuan, Hong-Lin Chu, Chihun Lee, Chih-Fan Liao, Hsuan-Yu Liu, Hong-Kai Hsu, Li-Chun Ko, Kuo-Hao Chen, Chao-Hsin Lu, Tsung-Ming Chen, YuLi Hsueh, Chunwei Chang, Yi-Hsien Cho, Chih-Hsien Shen, Yuan Sun, Eng-Chuan Low, Xudong Jiang, Deyong Hu, Weimin Shu, Jhy-Rong Chen, Jui-Lin Hsu, Chia-Jui Hsu, Jing-Hong Conan Zhan, Osama Shana'a, Guang-Kaai Dehng, George Chien

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2006

Design and anaylsis of a 2.5-Gbps optical receiver analog front-end in a 0.35-μm digital CMOS technology.

Wei-Zen Chen, Chao-Hsin Lu

IEEE Trans. Circuits Syst. I Regul. Pap., 2006

2002

A 2.5 Gbps CMOS optical receiver analog front-end.

Wei-Zen Chen, Chao-Hsin Lu

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002