Chao Chen
Orcid: 0000-0001-6488-224XAffiliations:
- Shenzhen Institutes of Advanced Technology (SIAT), CAS, China
According to our database1,
Chao Chen
authored at least 16 papers
between 2020 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
TIE: Fast Experiment-Driven ML-Based Configuration Tuning for In-Memory Data Analytics.
IEEE Trans. Computers, May, 2024
AnchorCapsule: A Datastream-Serving Post-Processor for Object Detection in Embedded Vision SoC.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024
Harmonizing Unets: Attention Fusion module in cascaded-Unets for low-quality OCT image fluid segmentation.
Comput. Biol. Medicine, 2024
Low-latency Buffering for Mixed-precision Neural Network Accelerator with MulTAP and FQPipe.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
PerFT-N: Low-overhead Permanent Fault-Tolerance Mechanism for Neural Processing Units.
Proceedings of the Great Lakes Symposium on VLSI 2024, 2024
2023
COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation Functions.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
An Energy-Efficient Method for Recurrent Neural Network Inference in Edge Cloud Computing.
Symmetry, 2022
2021
sEMG-Based Gesture Recognition Using GRU With Strong Robustness Against Forearm Posture.
Proceedings of the IEEE International Conference on Real-time Computing and Robotics, 2021
CNN-DMA: A Predictable and Scalable Direct Memory Access Engine for Convolutional Neural Network with Sliding-window Filtering.
Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021
OR-ML: Enhancing Reliability for Machine Learning Accelerator with Opportunistic Redundancy.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the AISS 2021: 3rd International Conference on Advanced Information Science and System, Sanya, China, November 26, 2021
Improving system latency of AI accelerator with on-chip pipelined activation preprocessing and multi-mode batch inference.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021
2020
Accelerating Atrous Convolution with Fetch-and-Jump Architecture for Activation Positioning.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
BBS: Micro-Architecture Benchmarking Blockchain Systems through Machine Learning and Fuzzy Set.
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
Proceedings of the CCRIS 2020: International Conference on Control, 2020