Chanh Tran

According to our database, Chanh Tran authored at least 5 papers between 1996 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A Fast-Lock, Jitter Filtering All-Digital DLL Based Burst-Mode Memory Interface.

Masum Hossain, Farrukh Aquil, Pak Shing Chau, Brian Tsang, Phuong Le, Jason Wei, Teva Stone, Barry Daly, Chanh Tran, John C. Eble, Kurt Knorpp, Jared Zerbe

IEEE J. Solid State Circuits, 2014

2012

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface.

Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface.

Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

IEEE J. Solid State Circuits, 2012

1999

A portable digital DLL for high-speed CMOS interface circuits.

Bruno W. Garlepp, Kevin S. Donnelly, Jun Kim, Pak Shing Chau, Jared L. Zerbe, Charlie Huang, Chanh Tran, Clemenz L. Portmann, Donald Stark, Yiu-Fai Chan, Thomas H. Lee, Mark A. Horowitz

IEEE J. Solid State Circuits, 1999

1996

A 660 MB/s interface megacell portable circuit in 0.3 μm-0.7 μm CMOS ASIC.

Kevin S. Donnelly, Yiu-Fai Chan, John T. C. Ho, Chanh Tran, Samir Patel, Benedict Lau, Jun Kim, Pak Shing Chau, Charlie Huang, Jason Wei, Leung Yu, Richard Tarver, Rakhee Kulkarni, Donald Stark, Mark Johnson

IEEE J. Solid State Circuits, 1996