Changnam Park
According to our database1,
Changnam Park
authored at least 7 papers
between 2017 and 2022.
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Bibliography
2022
A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit.
IEEE J. Solid State Circuits, 2022
2021
A Wide-Range Static Current-Free Current Mirror-Based LS With Logic Error Detection for Near-Threshold Operation.
IEEE J. Solid State Circuits, 2021
2019
Bitline Charge-Recycling SRAM Write Assist Circuitry for $V_{\mathrm{MIN}}$ Improvement and Energy Saving.
IEEE J. Solid State Circuits, 2019
A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 7nm FinFET SRAM using EUV lithography with dual write-driver-assist circuitry for low-voltage applications.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017