Changmin Sim

Orcid: 0009-0003-6748-1283

According to our database1, Changmin Sim authored at least 11 papers between 2023 and 2025.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

2023
2024
2025
0
1
2
3
4
5
6
7
8
9
1
8
2

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2025
A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM.
IEEE Trans. Circuits Syst. II Express Briefs, February, 2025

2024
A 25-Gb/s Single-Ended PAM-4 Transmitter With iPWM-Based FFE and RLM-Matched Voltage-Mode Driver for High-Speed Memory Interfaces.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2024

A 0.458-pJ/bit 24-Gb/s/pin Capacitively Driven PAM-4 Transceiver With PAM-Based Crosstalk Cancellation for High-Density Die-to-Die Interfaces.
IEEE J. Solid State Circuits, November, 2024

Single-Ended PAM-4 Transmitters With Data Bus Inversion and ZQ Calibration for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits, October, 2024

A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling.
IEEE Trans. Circuits Syst. II Express Briefs, September, 2024

A Wireline Transceiver With 3-bit per Symbol Using Common-Mode NRZ and Differential-Mode PAM-4 Signaling Techniques.
IEEE J. Solid State Circuits, August, 2024

A 13-Gb/s Single-Ended NRZ Receiver With 1-Sample Per 2-UI Using Data Edge Sampling for Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, July, 2024

A 10-Gb/s Wireline Receiver Using Linear Baud-Rate CDR and Analog Equalizer for Free Space Optical Communication Over 10- and 100-m Distances.
IEEE J. Solid State Circuits, June, 2024

A Single-Ended NRZ Receiver With Gain-Enhanced Active-Inductive CTLE and Reference-Selection DFE for Memory Interfaces.
IEEE J. Solid State Circuits, April, 2024

2023
A 4-GHz Ring-Oscillator-Based Digital Sub-Sampling PLL With Energy-Efficient Dual-Domain Phase Detector.
IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

A 25-Gb/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces.
IEEE J. Solid State Circuits, 2023


  Loading...