Changhwan Shin

Orcid: 0000-0001-6057-3773

According to our database¹, Changhwan Shin authored at least 20 papers between 2010 and 2024.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

Legend:

Book

In proceedings

Article

PhD thesis

Dataset

Other

Links

On csauthors.net:

Bibliography

2024

Column Row Convolutional Neural Network: Reducing Parameters for Efficient Image Processing.

[BibT_eX]

[DOI]

Neural Comput., April, 2024

2023

Comparative Study of Novel u-Shaped SOI FinFET Against Multiple-Fin Bulk/SOI FinFET.

[BibT_eX]

[DOI]

IEEE Access, 2023

2022

Strain-Dependent Photoacoustic Characteristics of Free-Standing Carbon-Nanocomposite Transmitters.

[BibT_eX]

[DOI]

Muhammad Faraz

Muhammad Awais Abbasi

Sensors, 2022

Impact of Chamber/Annealing Temperature on the Endurance Characteristic of Zr: HfO2 Ferroelectric Capacitor.

[BibT_eX]

[DOI]

Sensors, 2022

Quantitative Evaluation of Line-Edge Roughness in Various FinFET Structures: Bayesian Neural Network With Automatic Model Selection.

[BibT_eX]

[DOI]

IEEE Access, 2022

GAN-Based Framework for Unified Estimation of Process-Induced Random Variation in FinFET.

[BibT_eX]

[DOI]

IEEE Access, 2022

2021

Probabilistic Artificial Neural Network for Line-Edge-Roughness-Induced Random Variation in FinFET.

[BibT_eX]

[DOI]

Jaehyuk Lim

Jinwoong Lee

Changhwan Shin

IEEE Access, 2021

Abruptly-Switching MoS₂-Channel Atomic-Threshold-Switching Field-Effect Transistor With AgTi/HfO₂-Based Threshold Switching Device.

[BibT_eX]

[DOI]

IEEE Access, 2021

2020

Machine Learning (ML)-Based Model to Characterize the Line Edge Roughness (LER)-Induced Random Variation in FinFET.

[BibT_eX]

[DOI]

Jaehyuk Lim

Changhwan Shin

IEEE Access, 2020

2017

Layout engineering to suppress hysteresis of negative capacitance FinFET.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2016

Design Optimization for Process-Variation-Tolerant 22-nm FinFET-Based 6-T SRAM Cell with Worst-Case Sampling Method.

[BibT_eX]

[DOI]

Sangheon Oh

Changhwan Shin

IEICE Trans. Electron., 2016

Amorphous Indium Zinc Oxide Thin-Film Transistor with Steep Subthreshold Slope by Negative Capacitance.

[BibT_eX]

[DOI]

Karam Cho

Jaesung Jo

Changhwan Shin

IEICE Trans. Electron., 2016

2015

Impact of the double-patterning technique on the LER-induced threshold voltage variation in symmetric tunnel field-effect transistor.

[BibT_eX]

[DOI]

Seulki Park

Ju Han Lee

Changhwan Shin

IEICE Electron. Express, 2015

2014

Experimental demonstration of a ferroelectric FET using paper substrate.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

State-of-the-art silicon device miniaturization technology and its challenges.

[BibT_eX]

[DOI]

Changhwan Shin

IEICE Electron. Express, 2014

Analysis and modeling for random telegraph noise of GIDL current in saddle MOSFET for DRAM application.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

2013

Effect of double-patterning and double-etching on the line-edge-roughness of multi-gate bulk MOSFETs.

[BibT_eX]

[DOI]

In Jun Park

Changhwan Shin

IEICE Electron. Express, 2013

Comparative study in work-function variation: Gaussian vs. Rayleigh distribution for grain size.

[BibT_eX]

[DOI]

Hyohyun Nam

Changhwan Shin

IEICE Electron. Express, 2013

2012

Quasi-Planar Tri-gate (QPT) bulk CMOS technology for single-port SRAM application.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2010

SRAM design in fully-depleted SOI technology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Changhwan Shin

Timeline

Legend:

Links

On csauthors.net:

Bibliography

Loading...