Chang Xue
Orcid: 0000-0003-1566-5809
According to our database1,
Chang Xue
authored at least 5 papers
between 2022 and 2024.
Collaborative distances:
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Bibliography
2024
A 768.7-2124.2 TOPS/W Time-Domain Computing-in-Memory Macro With Low Static Leakage and Precision-Configurable TDC.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
An eDRAM-Based Computing-in-Memory Macro With Full-Valid-Storage and Channel-Wise-Parallelism for Depthwise Neural Network.
IEEE Trans. Circuits Syst. II Express Briefs, May, 2024
A Dual-Branch Autoencoder Network for Underwater Low-Light Polarized Image Enhancement.
Remote. Sens., April, 2024
2022
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022