Chang Woo Kang
According to our database1,
Chang Woo Kang
authored at least 11 papers
between 2002 and 2007.
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Bibliography
2007
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007
2006
Gate Sizing and Replication to Minimize the Effects of Virtual Ground Parasitic Resistances in MTCMOS Designs.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006
Low-power clustering with minimum logic replication for coarse-grained, antifuse based FPGAs.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
2005
A Prototype Processing-In-Memory (PIM) Chip for the Data-Intensive Architecture (DIVA) System.
J. VLSI Signal Process., 2005
A Leakage-aware Low Power Technology Mapping Algorithm Considering the Hot-Carrier Effect.
J. Low Power Electron., 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
Technology mapping for low leakage power and high speed with hot-carrier effect consideration.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
2002
Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Proceedings of the 16th international conference on Supercomputing, 2002