Chang-Un Park

Orcid: 0009-0000-2722-4651

According to our database1, Chang-Un Park authored at least 5 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
A 1.5-MHz BW 81.2-dB SNDR Dual-Residue Pipeline ADC With a Fully Dynamic Noise-Shaping Interpolating-SAR ADC.
IEEE J. Solid State Circuits, August, 2024

A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023
A 12-bit 1GS/s Current-Steering DAC with Paired Current Source Switching Background Mismatch Calibration.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

An 81.2dB-SNDR Dual-Residue Pipeline ADC with a 2nd- Order Noise-Shaping Interpolating SAR ADC.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2019
A Single-Supply Buffer-Embedding SAR ADC with Skip-Reset having Inherent Chopping Capability.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019


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