Chang-Kyo Lee
Orcid: 0000-0001-6990-5869
According to our database1,
Chang-Kyo Lee
authored at least 23 papers
between 2007 and 2023.
Collaborative distances:
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Bibliography
2023
KSII Trans. Internet Inf. Syst., March, 2023
2021
An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques.
IEEE J. Solid State Circuits, 2021
2020
Interpretation of Impact-Echo Testing Data from a Fire-Damaged Reinforced Concrete Slab Using a Discrete Layered Concrete Damage Model.
Sensors, 2020
IEEE J. Solid State Circuits, 2020
22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
Noise analysis of replica driving technique and its verification to 12-bit 200 MS/s pipelined ADC.
IET Circuits Devices Syst., 2019
A 5Gb/s/pin 16Gb LPDDR4/4X Reconfigurable SDRAM with Voltage-High Keeper and a Prediction-based Fast-tracking ZQ Calibration.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2018
Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM.
IEEE J. Solid State Circuits, 2018
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Performance Test of LTE-R Railway Wireless Communication at High-Speed (350 km/h) Environments.
Proceedings of the Tenth International Conference on Ubiquitous and Future Networks, 2018
2017
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2015
A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface.
Proceedings of the Symposium on VLSI Circuits, 2015
2014
A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2014
Proceedings of the Three-Dimensional Image Processing, 2014
2013
A Replica-Driving Technique for High Performance SC Circuits and Pipelined ADC Design.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
2011
IEEE J. Solid State Circuits, 2011
2010
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007