Chandramouli V. Kashyap

According to our database, Chandramouli V. Kashyap authored at least 28 papers between 2000 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables.

Subhadip Ghosh, Endalk Y. Gebru, Chandramouli V. Kashyap, Ramesh Harjani, Sachin S. Sapatnekar

CoRR, February, 2025

2021

DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks.

Ahmet Faruk Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020

MLParest: Machine Learning based Parasitic Estimation for Custom Circuit Design.

Brett Shook, Prateek Bhansali, Chandramouli V. Kashyap, Chirayu Amin, Siddhartha Joshi

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2016

Guest Editors' Introduction Challenges and Opportunities in Analog/Mixed-Signal CAD.

Xin Li, Chandramouli V. Kashyap, Chris J. Myers

IEEE Des. Test, 2016

2010

Pessimism Reduction in Coupling-Aware Static Timing Analysis Using Timing and Logic Filtering.

Debasish Das, Kip Killpack, Chandramouli V. Kashyap, Abhijit Jas, Hai Zhou

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

2009

Quantifying robustness metrics in parameterized static timing analysis.

Khaled R. Heloue, Chandramouli V. Kashyap, Farid N. Najm

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

2008

Silicon feedback to improve frequency of high-performance microprocessors: an overview.

Chandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

A "true" electrical cell model for timing, noise, and power grid verification.

Noel Menezes, Chandramouli V. Kashyap, Chirayu S. Amin

Proceedings of the 45th Design Automation Conference, 2008

A framework for block-based timing sensitivity analysis.

Sanjay V. Kumar, Chandramouli V. Kashyap, Sachin S. Sapatnekar

Proceedings of the 45th Design Automation Conference, 2008

2007

A nonlinear cell macromodel for digital applications.

Chandramouli V. Kashyap, Chirayu S. Amin, Noel Menezes, Eli Chiprout

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Silicon Speedpath Measurement and Feedback into EDA flows.

Kip Killpack, Chandramouli V. Kashyap, Eli Chiprout

Proceedings of the 44th Design Automation Conference, 2007

2006

Fast Interconnect and Gate Timing Analysis for Performance Optimization.

Soroush Abbaspour, Massoud Pedram, Amir H. Ajami, Chandramouli V. Kashyap

IEEE Trans. Very Large Scale Integr. Syst., 2006

A multi-port current source model for multiple-input switching effects in CMOS library cells.

Chirayu S. Amin, Chandramouli V. Kashyap, Noel Menezes, Kip Killpack, Eli Chiprout

Proceedings of the 43rd Design Automation Conference, 2006

2005

A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis.

Haihua Su, David Widiger, Chandramouli V. Kashyap, Frank Liu, Byron Krauter

Proceedings of the 42nd Design Automation Conference, 2005

2004

A delay metric for RC circuits based on the Weibull distribution.

Frank Liu, Chandramouli V. Kashyap, Charles J. Alpert

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Closed-form expressions for extending step delay and slew metrics to ramp inputs for RC trees.

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Closed-form delay and slew metrics made easy.

Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique.

Charles J. Alpert, Chris C. N. Chu, Gopal Gandham, Milos Hrkic, Jiang Hu, Chandramouli V. Kashyap, Stephen T. Quay

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

2003

Closed form expressions for extending step delay and slew metrics to ramp inputs.

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan

Proceedings of the 2003 International Symposium on Physical Design, 2003

Realizable reduction of RLC circuits using node elimination.

Masud H. Chowdhury, Chirayu S. Amin, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Block-based Static Timing Analysis with Uncertainty.

Anirudh Devgan, Chandramouli V. Kashyap

Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Delay and slew metrics using the lognormal distribution.

Charles J. Alpert, Frank Liu, Chandramouli V. Kashyap, Anirudh Devgan

Proceedings of the 40th Design Automation Conference, 2003

2002

PERI: a technique for extending delay and slew metrics to ramp inputs.

Chandramouli V. Kashyap, Charles J. Alpert, Frank Liu, Anirudh Devgan

Proceedings of the 8th ACM/IEEE International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2002

Performance analysis of deep sub micron VLSI circuits in the presence of self and mutual inductance.

Masud H. Chowdhury, Yehea I. Ismail, Chandramouli V. Kashyap, Byron Krauter

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001

RC delay metrics for performance optimization.

Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

2000

A two moment RC delay metric for performance optimization.

Charles J. Alpert, Anirudh Devgan, Chandramouli V. Kashyap

Proceedings of the 2000 International Symposium on Physical Design, 2000

An "Effective" Capacitance Based Delay Metric for RC Interconnect.

Chandramouli V. Kashyap, Charles J. Alpert, Anirudh Devgan

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

A realizable driving point model for on-chip interconnect with inductance.

Chandramouli V. Kashyap, Byron Krauter

Proceedings of the 37th Conference on Design Automation, 2000