Chandramouli N. Amarnath
Orcid: 0000-0001-9938-2157
According to our database1,
Chandramouli N. Amarnath
authored at least 26 papers
between 2020 and 2024.
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Bibliography
2024
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2024
CoRR, 2024
A Novel Hyperdimensional Computing Framework for Online Time Series Forecasting on the Edge.
CoRR, 2024
Error Resilient Hyperdimensional Computing Using Hypervector Encoding and Cross-Clustering.
Proceedings of the 42nd IEEE VLSI Test Symposium, 2024
ADARE-HD: Adaptive-Resolution Framework for Efficient Object Detection and Tracking via HD-Computing.
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
Proceedings of the 67th IEEE International Midwest Symposium on Circuits and Systems, 2024
DeepER-HD: An Error Resilient HyperDimensional Computing Framework with DNN Front-End for Feature Selection.
Proceedings of the 25th IEEE Latin American Test Symposium, 2024
Proceedings of the 30th IEEE International Symposium on On-Line Testing and Robust System Design, 2024
Post-Manufacture Criticality-Aware Gain Tuning of Timing Encoded Spiking Neural Networks for Yield Recovery.
Proceedings of the IEEE European Test Symposium, 2024
AMS Test Stimulus Generation and Response Analysis Using Hyperdimensional Clustering: Minimizing Misclassification Rate.
Proceedings of the IEEE European Test Symposium, 2024
Learning Assisted Post-Manufacture Testing and Tuning of RRAM-Based DNNs for Yield Recovery.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
Signature Driven Post-Manufacture Testing and Tuning of RRAM Spiking Neural Networks for Yield Recovery.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024
2023
Proceedings of the 24th IEEE Latin American Test Symposium, 2023
OATT: Outlier Oriented Alternative Testing and Post-Manufacture Tuning of Mixed-Signal/RF Circuits and Systems.
Proceedings of the IEEE International Test Conference, 2023
Secure Control Loop Execution of Cyber-Physical Devices Using Predictive State Space Checks.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
A Resilience Framework for Synapse Weight Errors and Firing Threshold Perturbations in RRAM Spiking Neural Networks.
Proceedings of the IEEE European Test Symposium, 2023
Error Resilient Transformers: A Novel Soft Error Vulnerability Guided Approach to Error Checking and Suppression.
Proceedings of the IEEE European Test Symposium, 2023
2022
Low Power Neural Network Accelerators Using Collaborative Weight Tuning and Shared Shift-Add optimization.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Efficient Low Cost Alternative Testing of Analog Crossbar Arrays for Deep Neural Networks.
Proceedings of the IEEE International Test Conference, 2022
Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022
2021
CoRR, 2021
Hierarchical Failure Modeling and Machine Learning Assisted Correction of Electro-Mechanical Subsystem Failures in Autonomous Vehicles.
Proceedings of the IEEE International Test Conference, 2021
Addressing Soft Error and Security Threats in DNNs Using Learning Driven Algorithmic Checks.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
2020
Concurrent Error Detection in Embedded Digital Control of Nonlinear Autonomous Systems Using Adaptive State Space Checks.
Proceedings of the IEEE International Test Conference, 2020
Encoded Check Driven Concurrent Error Detection in Particle Filters for Nonlinear State Estimation.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020