ChandraKanth R. Chappidi
Orcid: 0000-0002-4350-1185
According to our database1,
ChandraKanth R. Chappidi
authored at least 10 papers
between 2015 and 2022.
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Collaborative distances:
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Bibliography
2022
A 4 × 4 Steerable 14-dBm EIRP Array on CMOS at 0.41 THz With a 2-D Distributed Oscillator Network.
IEEE J. Solid State Circuits, 2022
2020
Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Receivers and Antennas.
IEEE J. Solid State Circuits, 2020
Antenna Preprocessing and Element-Pattern Shaping for Multi-Band mmWave Arrays: Multi-Port Transmitters and Antennas.
IEEE J. Solid State Circuits, 2020
29.9 A 4×4 Distributed Multi-Layer Oscillator Network for Harmonic Injection and THz Beamforming with 14dBm EIRP at 416GHz in a Lensless 65nm CMOS IC.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
A 26-42 GHz Broadband, Back-off Efficient and Vswr Tolerant CMOS Power Amplifier Architecture for 5G Applications.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Simultaneously Broadband and Back-Off Efficient mm-Wave PAs: A Multi-Port Network Synthesis Approach.
IEEE J. Solid State Circuits, 2018
2017
Frequency Reconfigurable mm-Wave Power Amplifier With Active Impedance Synthesis in an Asymmetrical Non-Isolated Combiner: Analysis and Design.
IEEE J. Solid State Circuits, 2017
2016
20.2 A frequency-reconfigurable mm-Wave power amplifier with active-impedance synthesis in an asymmetrical non-isolated combiner.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2015
Methods for finding globally maximum-efficiency impedance matching networks with lossy passives.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015