Chandrajit Debnath

According to our database, Chandrajit Debnath authored at least 5 papers between 2007 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

A 0.065-mm² 19.8-mW Single-Channel Calibration-Free 12-b 600-MS/s ADC in 28-nm UTBB FD-SOI Using FBB.

Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik

IEEE J. Solid State Circuits, 2017

2016

A 0.065mm² 19.8mW single channel calibration-free 12b 600MS/s ADC in 28nm UTBB FDSOI using FBB.

Ashish Kumar, Chandrajit Debnath, Pratap Narayan Singh, Vivek Bhatia, Shivani Chaudhary, Vigyan Jain, Stéphane Le Tual, Rakesh Malik

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016

2010

A 6 bit 800MHz TIADC Based on Successive Approximation in 65nm Standard CMOS Process.

Arunkumar Salimath, Chandrajit Debnath, Kallol Chatterjee, Sushanta K. Mandal

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

2008

A 1.2v 11b 100Msps 15mW ADC realized using 2.5b pipelined stage followed by time interleaved SAR in 65nm digital CMOS process.

Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik

Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007

20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process.

Pratap Narayan Singh, Ashish Kumar, Chandrajit Debnath, Rakesh Malik

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007