Chandra Shekhar
Affiliations:- Central Electronics Engineering Research Institute (CEERI), Pilani, India
According to our database1,
Chandra Shekhar
authored at least 29 papers
between 1992 and 2022.
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Bibliography
2022
Area, Speed and Power Optimized Implementation of a Band-Pass FIR Filter Using High-Level Synthesis.
Wirel. Pers. Commun., 2022
2021
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm.
Microprocess. Microsystems, 2021
Power- and Area-Optimized High-Level Synthesis Implementation of a Digital Down Converter for Software-Defined Radio Applications.
Circuits Syst. Signal Process., 2021
High-speed and area-efficient Sobel edge detector on field-programmable gate array for artificial intelligence and machine learning applications.
Comput. Intell., 2021
2020
Speed optimal FPGA implementation of the encryption algorithms for telecom applications.
Microprocess. Microsystems, 2020
High-Level synthesis assisted design and verification framework for automotive radar processors.
Microprocess. Microsystems, 2020
2019
2017
Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems.
J. Imaging, 2017
Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform.
J. Imaging, 2017
2015
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications.
Proceedings of the 28th International Conference on VLSI Design, 2015
An embedded framework for accurate object localization using center of gravity measure with mean shift procedure.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015
2014
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
FPGA-based real-time object tracker using modified particle filtering and SAD computation.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
Automatic real-time extraction of focused regions in a live video stream using edge width information.
Proceedings of the 18th International Symposium on VLSI Design and Test, 2014
2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
2010
J. Signal Process. Syst., 2010
Proceedings of the Information and Communication Technologies - International Conference, 2010
2009
Dual channel addition based FFT processor architecture for signal and image processing.
Int. J. High Perform. Syst. Archit., 2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load.
Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, 2009
2008
VLSI Design, 2008
A High-Speed Radix-64 Parallel Multiplier Using a Novel Hardware Implementation Approach for Partial Product Generation Based on Redundant Binary Arithmetic.
Proceedings of the First International Conference on Emerging Trends in Engineering and Technology, 2008
2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
2004
Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
2001
High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
1992
Proceedings of the Fifth International Conference on VLSI Design, 1992
Proceedings of the Fifth International Conference on VLSI Design, 1992
Proceedings of the Fifth International Conference on VLSI Design, 1992