Chandra Babu Dara

According to our database, Chandra Babu Dara authored at least 4 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2017

Delay Analysis for Current Mode Threshold Logic Gate Designs.

Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas

IEEE Trans. Very Large Scale Integr. Syst., 2017

2013

Low power and high speed current-mode memristor-based TLGs.

Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

2012

Delay Analysis for an N-Input Current Mode Threshold Logic Gate.

Chandra Babu Dara, Themistoklis Haniotakis, Spyros Tragoudas

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

2011

A Metric for Weight Assignment to Optimize the Performance of MOBILE Threshold Logic Gate.

Chandra Babu Dara, Spyros Tragoudas, Themistoklis Haniotakis

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011