Chandan Karfa

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2024

LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification.

[BibT_eX]

[DOI]

Karthik Maddala

Bhabesh Mali

CoRR, 2024

ERS: Energy-efficient Real-time DAG Scheduling on Uniform Multiprocessor Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

SRIL: Securing Registers from Information Leakage at Register Transfer Level.

[BibT_eX]

[DOI]

Vignesh Ravichandra Rao

Thockchom Birjit Singha

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

Evaluating the Robustness of Large scale eFPGA-based Hardware Redaction.

[BibT_eX]

[DOI]

Praveen Karmakar

Marpina Bharani

Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

NoBALL: A Novel BDD-based Attack against Logic Locking.

[BibT_eX]

[DOI]

Sukanta Bhattacharjee

Proceedings of the IEEE International Test Conference in Asia, 2024

ChIRAAG: ChatGPT Informed Rapid and Automated Assertion Generation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

RTL Simulation Acceleration with Machine Learning Models.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Quality Electronic Design, 2024

2023

TMDS: Temperature-aware Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., November, 2023

Translation Validation of Information Leakage of Compiler Optimizations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Energy-Aware Real-Time Scheduling of Multiple Periodic DAGs on Heterogeneous Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

An Investigation into the Security of Register Allocation with Spilling and Splitting.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

2022

Quantifying Information Leakage for Security Verification of Compiler Optimizations.

[BibT_eX]

[DOI]

Abhik Paul

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

FastSim: A Fast Simulation Framework for High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

BLAST: Belling the Black-Hat High-Level Synthesis Tool.

[BibT_eX]

[DOI]

Mohammed Abderehman

Rupak Gupta

Theegala Rakesh Reddy

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

PRESTO: A Penalty-Aware Real-Time Scheduler for Task Graphs on Heterogeneous Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Secure Register Allocation for Trusted Code Generation.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC.

[BibT_eX]

[DOI]

IEEE Embed. Syst. Lett., 2022

Accelerating NoC Verification Using a Complete Model and Active Window.

[BibT_eX]

[DOI]

Santosh Biswas

IEEE Access, 2022

Corruption Exposes You: Statistical Key Recovery from Compound Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

DEEQ: Data-driven End-to-End EQuivalence Checking of High-level Synthesis.

[BibT_eX]

[DOI]

Mohammed Abderehman

Theegala Rakesh Reddy

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Performance-Effective DAG Scheduling for Heterogeneous Distributed Systems.

[BibT_eX]

[DOI]

Proceedings of the ICDCN '22: 23rd International Conference on Distributed Computing and Networking, Delhi, AA, India, January 4, 2022

GAUR: Genetic Algorithm based Unlocking of Register Transfer Level Locking.

[BibT_eX]

[DOI]

Gagan Gayari

Abdul Khader Thalakkattu Moosa

Prithwijit Guha

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

ImageSpec: Efficient High-Level Synthesis of Image Processing Applications.

[BibT_eX]

[DOI]

Nilotpola Sarma

Proceedings of the 25th Euromicro Conference on Digital System Design, 2022

2021

HMDS: A Makespan Minimizing DAG Scheduler for Heterogeneous Distributed Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2021

VP_TT: A value propagation based equivalence checker for testability transformations.

[BibT_eX]

[DOI]

Sachin Kumar Maddheshiya

IET Softw., 2021

Reverse Engineering Register to Variable Mapping in High-level Synthesis.

[BibT_eX]

[DOI]

Mohammed Abderehman

Rupak Gupta

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

HOST: HLS Obfuscations against SMT ATtack.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock.

[BibT_eX]

[DOI]

Santosh Biswas

IEEE Trans. Very Large Scale Integr. Syst., 2020

Verification of Scheduling of Conditional Behaviors in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.

[BibT_eX]

[DOI]

CoRR, 2020

Automatic Inverse Operation Detection and its Impact in High-level Synthesis.

[BibT_eX]

[DOI]

Pankaj Kumar Kalita

Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Is Register Transfer Level Locking Secure?

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SAT Based Partial Attack on Compound Logic Locking.

[BibT_eX]

[DOI]

Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2020

2019

Translation Validation of Code Motion Transformations Involving Loops.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Counter-example generation procedure for path-based equivalence checkers.

[BibT_eX]

[DOI]

IET Softw., 2019

Verification of parallelising transformations of KPN models.

[BibT_eX]

[DOI]

Chittaranjan Mandal

IET Cyper-Phys. Syst.: Theory & Appl., 2019

A Quick Introduction to Functional Verification of Array-Intensive Programs.

[BibT_eX]

[DOI]

CoRR, 2019

Improving Performance of a Path-Based Equivalence Checker Using Counter-Examples.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

User Guided Register Manipulation in Digital Circuits.

[BibT_eX]

[DOI]

Rajesh Kumar Jha

Proceedings of the VLSI Design and Test - 23rd International Symposium, 2019

Formal Verification of Optimizing Transformations during High-level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 12th Innovations on Software Engineering Conference (formerly known as India Software Engineering Conference), 2019

2018

Compiler-agnostic Translation Validation.

[BibT_eX]

[DOI]

Proceedings of the 11th Innovations in Software Engineering Conference, ISEC 2018, Hyderabad, India, February 09, 2018

Automatic detection of inverse operations while avoiding loop unrolling.

[BibT_eX]

[DOI]

Proceedings of the 40th International Conference on Software Engineering: Companion Proceeedings, 2018

2017

xMAS Based Accurate Modeling and Progress Verification of NoCs.

[BibT_eX]

[DOI]

Santosh Biswas

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Translation Validation of Loop Invariant Code Optimizations Involving False Computations.

[BibT_eX]

[DOI]

Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2014

Verification of Code Motion Techniques Using Value Propagation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014

2013

Verification of Loop and Arithmetic Transformations of Array-Intensive Behaviors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Verification of KPN Level Transformations.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

2012

Formal verification of code motion techniques using data-flow-driven equivalence checking.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

A Value Propagation Based Equivalence Checking Method for Verification of Code Motion Techniques.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Electronic System Design, 2012

2011

Verification of Register Transfer Level Low Power Transformations.

[BibT_eX]

[DOI]

Chitta Mandal

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Equivalence Checking of Array-Intensive Programs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

Verification of Datapath and Controller Generation Phase in High-Level Synthesis of Digital Circuits.

[BibT_eX]

[DOI]

Chitta Mandal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Data-Flow Driven Equivalence Checking for Verification of Code Motion Techniques.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

2008

An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computing: Theory and Applications (ICCTA 2007), 2007

Hand-in-hand verification of high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006

Verification of Scheduling in High-level Synthesis.

[BibT_eX]

[DOI]

S. R. Pentakota

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Formal Verification Method of Scheduling in High-level Synthesis.

[BibT_eX]

[DOI]

S. R. Pentakota