Chan-Hsiang Weng

According to our database, Chan-Hsiang Weng authored at least 12 papers between 2011 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

A 71. 4dB SNDR 30MHz BW Continuous-Time Delta-sigma Modulator Using a Time-Interleaved Noise-Shaping Quantizer in 12-nm CMOS.

Chan-Hsiang Weng, Tzu-An Wei, Hung-Yi Hsieh, Su-Hao Wu, Ting-Yang Wang

Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019

An 8 × - OSR 25MHz-BW 79.4dB/74dB DR/SNDR CT Δ σ Modulator Using 7b Linearized Segmented DACs with Digital Noise-Coupling-Compensation Filter in 7nm FinFET CMOS.

Tien-Yu Lo, Chan-Hsiang Weng, Hung-Yi Hsieh, Yun-Shiang Shu, Pao-Cheng Chiu

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2017

A 1-V 5-MHz Bandwidth 68.3-dB SNDR Continuous-Time Delta-Sigma Modulator With a Feedback-Assisted Quantizer.

Chan-Hsiang Weng, Yung-Yu Lin, Tsung-Hsien Lin

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

2016

A Continuous-Time Delta-Sigma Modulator Using ELD-Compensation-Embedded SAB and DWA-Inherent Time-Domain Quantizer.

Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Tsung-Hsien Lin

IEEE J. Solid State Circuits, 2016

2015

A CMOS Thermistor-Embedded Continuous-Time Delta-Sigma Temperature Sensor With a Resolution FoM of 0.65 pJ°C².

Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin

IEEE J. Solid State Circuits, 2015

A 127 fJ/conv. continuous-time delta-sigma modulator with a DWA-embedded two-step time-domain quantizer.

Chan-Hsiang Weng, Tzu-An Wei, Tsung-Hsien Lin

Proceedings of the VLSI Design, Automation and Test, 2015

A 13-MHz 68-dB SNDR CTDSM using SAB loop filter and interpolating flash quantizer with random-skip IDWA function in 90-nm CMOS.

Chan-Hsiang Weng, Wei-Hsiang Huang, Erkan Alpman, Tsung-Hsien Lin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

2014

A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator.

Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2014

An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS.

Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Yi-Ting Tseng, Tsung-Hsien Lin

Proceedings of the Symposium on VLSI Circuits, 2014

A CMOS thermistor-embedded continuous-time delta-sigma temperature sensor with a resolution of 0.01 °C.

Chan-Hsiang Weng, Chun-Kuan Wu, Tsung-Hsien Lin

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013

A low-power dual-mode continuous-time delta-sigma modulator with a folded quantizer.

Chen-Chien Lin, Chan-Hsiang Weng, Tsung-Hsien Lin

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

2011

A 0.89-mW 1-MHz 62-dB SNDR Continuous-Time Delta-Sigma Modulator With an Asynchronous Sequential Quantizer and Digital Excess-Loop-Delay Compensation.

Chan-Hsiang Weng, Chen-Chien Lin, Yu-Cheng Chang, Tsung-Hsien Lin

IEEE Trans. Circuits Syst. II Express Briefs, 2011