Chan-Ho Kye
According to our database1,
Chan-Ho Kye
authored at least 6 papers
between 2019 and 2024.
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Bibliography
2024
Design Methodology for Compact Single-Channel 3-Stage Capacitor-Array-Assisted Charge-Injection DAC-Based SAR ADC.
IEEE Trans. Circuits Syst. I Regul. Pap., November, 2024
2023
A 0.000261 mm<sup>2</sup> Single-Channel 1 GS/s 8-Bit 3-Stage Capacitor Array-Assisted Charge-Injection DAC-Based SAR ADC in 28 nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2020
A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2020
A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
2019
A 370-fJ/b, 0.0056 mm<sup>2</sup>/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop.
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A Synthesizable Digital AOT 4-Phase Buck Voltage Regulator for Digital Systems with 0.0054mm<sup>2</sup> Controller and 80ns Recovery Time.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019