Champaka Ramachandran

According to our database, Champaka Ramachandran authored at least 8 papers between 1991 and 1994.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1994

Combined topological and functionality-based delay estimation using a layout-driven approach for high-level applications.

Champaka Ramachandran, Fadi J. Kurdahi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

On the intrinsic Rent parameter and spectra-based partitioning methodologies.

Lars W. Hagen, Andrew B. Kahng, Fadi J. Kurdahi, Champaka Ramachandran

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

An Empirical Study on the Effects of Physical Design in High-Level Synthesis.

Pradip K. Jha, Champaka Ramachandran, Nikil D. Dutt, Fadi J. Kurdahi

Proceedings of the Seventh International Conference on VLSI Design, 1994

A performance driven logic synthesis system using delay estimator.

Yulin Chen, Wei Kang Tsai, Fadi J. Kurdahi, Tzong-Dar Her, Champaka Ramachandran

Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

Incorporating the Controller Effects During Register Transfer Level Synthesis.

Champaka Ramachandran, Fadi J. Kurdahi

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

1993

Evaluating layout area tradeoffs for high level applications.

Fadi J. Kurdahi, Champaka Ramachandran

IEEE Trans. Very Large Scale Integr. Syst., 1993

1992

Accurate layout area and delay modeling for system level design.

Champaka Ramachandran, Fadi J. Kurdahi, Daniel Gajski, Allen C.-H. Wu, Viraphol Chaiyakul

Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991

LAST: a Layout Area and Shape function esTimator for high level applications.

Fadi J. Kurdahi, Champaka Ramachandran

Proceedings of the conference on European design automation, 1991