Chak-Wa Pui

According to our database, Chak-Wa Pui authored at least 16 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

TOFU: A Two-Step Floorplan Refinement Framework for Whitespace Reduction.

Shixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang, Yu Huang, Jianye Hao

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Heterogeneous Graph Neural Network-Based Imitation Learning for Gate Sizing Acceleration.

Xinyi Zhou, Junjie Ye, Chak-Wa Pui, Kun Shao, Guangliang Zhang, Bin Wang, Jianye Hao, Guangyong Chen, Pheng-Ann Heng

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2021

Multi-FPGA Co-optimization: Hybrid Routing and Competitive-based Time Division Multiplexing Assignment.

Dan Zheng, Xiaopeng Zhang, Chak-Wa Pui, Evangeline F. Y. Young

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

Lagrangian Relaxation-Based Time-Division Multiplexing Optimization for Multi-FPGA Systems.

Chak-Wa Pui, Evangeline F. Y. Young

ACM Trans. Design Autom. Electr. Syst., 2020

Simultaneous Reconnection Surgery Technique of Routing With Machine Learning-Based Acceleration.

Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search.

Gengjie Chen, Chak-Wa Pui, Haocheng Li, Evangeline F. Y. Young

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CUGR: Detailed-Routability-Driven 3D Global Routing with Probabilistic Resource Model.

Jinwei Liu, Chak-Wa Pui, Fangzhou Wang, Evangeline F. Y. Young

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

An Analytical Approach for Time-Division Multiplexing Optimization in Multi-FPGA based Systems.

Chak-Wa Pui, Gang Wu, Freddy Y. C. Mang, Evangeline F. Y. Young

Proceedings of the 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, 2019

Device Layer-Aware Analytical Placement for Analog Circuits.

Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun, David Z. Pan

Proceedings of the 2019 International Symposium on Physical Design, 2019

Detailed routing by sparse grid graph and minimum-area-captured path search.

Gengjie Chen, Chak-Wa Pui, Haocheng Li, Jingsong Chen, Bentian Jiang, Evangeline F. Y. Young

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.

Gengjie Chen, Chak-Wa Pui, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Evangeline F. Y. Young, Bei Yu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Simultaneous Timing Driven Tree Surgery in Routing with Machine Learning-based Acceleration.

Peishan Tu, Chak-Wa Pui, Evangeline F. Y. Young

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

A two-step search engine for large scale boolean matching under NP3 equivalence.

Chak-Wa Pui, Peishan Tu, Haocheng Li, Gengjie Chen, Evangeline F. Y. Young

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).

Chak-Wa Pui, Gengjie Chen, Yuzhe Ma, Evangeline F. Y. Young, Bei Yu

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.

Chak-Wa Pui, Gengjie Chen, Wing-Kai Chow, Ka-Chun Lam, Jian Kuang, Peishan Tu, Hang Zhang, Evangeline F. Y. Young, Bei Yu

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Legalization algorithm for multiple-row height standard cell design.

Wing-Kai Chow, Chak-Wa Pui, Evangeline F. Y. Young

Proceedings of the 53rd Annual Design Automation Conference, 2016