César Fuguet Tortolero

Orcid: 0000-0003-0656-2023

According to our database1, César Fuguet Tortolero authored at least 14 papers between 2015 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
Xvpfloat: RISC-V ISA Extension for Variable Extended Precision Floating Point Computation.
IEEE Trans. Computers, July, 2024

Breaking the Memory Wall with a Flexible Open-Source L1 Data-Cache.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023
HPDcache: Open-Source High-Performance L1 Data Cache for RISC-V Cores.
Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

2022
Accelerating Variants of the Conjugate Gradient with the Variable Precision Processor.
Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022

2021
IntAct: A 96-Core Processor With Six Chiplets 3D-Stacked on an Active Interposer With Distributed Interconnects and Integrated Power Management.
IEEE J. Solid State Circuits, 2021

Storage Class Memory with Computing Row Buffer: A Design Space Exploration.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
2.3 A 220GOPS 96-Core Processor with 6 Chiplets 3D-Stacked on an Active Interposer Offering 0.6ns/mm Latency, 3Tb/s/mm<sup>2</sup> Inter-Chiplet Interconnects and 156mW/mm<sup>2</sup>@ 82%-Peak-Efficiency DC-DC Converters.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

POPSTAR: a Robust Modular Optical NoC Architecture for Chiplet-based 3D Integrated Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
WAVES: Wavelength Selection for Power-Efficient 2.5D-Integrated Photonic NoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
A 29 Gops/Watt 3D-Ready 16-Core Computing Fabric with Scalable Cache Coherent Architecture Using Distributed L2 and Adaptive L3 Caches.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018

2017
Trace-driven exploration of sharing set management strategies for cache coherence in manycores.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A Programmable Inbound Transfer Processor for Active Messages in Embedded Multicore Systems.
Proceedings of the Euromicro Conference on Digital System Design, 2017

A Method for Fast Evaluation of Sharing Set Management Strategies in Cache Coherence Protocols.
Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2015
Introduction of Fault-Tolerance Mechanisms for Permanent Failures in Coherent Shared-Memory Many-Core Architectures. (Introduction de mécanismes de tolérance aux pannes franches dans les architectures de processeur « many-core » à mémoire partagée cohérente).
PhD thesis, 2015


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