César A. M. Marcon

David Freitas Moura Mota

Alexandre Coelho

Proceedings of the 13th Latin-American Symposium on Dependable and Secure Computing, 2024

2023

A Triple Burst Error Correction Based on Region Selection Code.

[BibT_eX]

[DOI]

Felipe G. A. e Silva

IEEE Trans. Very Large Scale Integr. Syst., August, 2023

Exploration and Analysis of Combinations of Hamming Codes in 32-bit Memories.

[BibT_eX]

[DOI]

CoRR, 2023

EMPC-SA: Error Correction Scheme using Modified Product Code for Space Applications.

[BibT_eX]

[DOI]

Proceedings of the XIII Brazilian Symposium on Computing Systems Engineering, 2023

Memory Controller with Adaptive ECC for Reliable System Operation.

[BibT_eX]

[DOI]

Proceedings of the 36th SBC/SBMicro/IEEE/ACM Symposium on Integrated Circuits and Systems Design, 2023

Blockchain Applied In Decentralization of Ground Stations To Educational Nanosatellites.

[BibT_eX]

[DOI]

Edilson Filho

Ayalon Angelo de Moraes Filho

Proceedings of the 24th IEEE Latin American Test Symposium, 2023

LifeSeniorProfile: A Multisensor Dataset for Elderly Real-time Activity Track.

[BibT_eX]

[DOI]

Maicon Diogo Much

Julio Alexander Sieg

Vanessa de Moura Bartoski

Guilherme Schreiber

Ayalon Angelo de Moraes Filho

Proceedings of the 16th International Joint Conference on Biomedical Engineering Systems and Technologies, 2023

Methods to Estimate Respiratory Rate Using the Photoplethysmography Signal.

[BibT_eX]

[DOI]

Guilherme Schreiber

Julio Alexander Sieg

Maicon Diogo Much

Vanessa de Moura Bartoski

Proceedings of the 16th International Joint Conference on Biomedical Engineering Systems and Technologies, 2023

2022

Configurable Fast Block Partitioning for VVC Intra Coding Using Light Gradient Boosting Machine.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2022

OPCoSA: an Optimized Product Code for space applications.

[BibT_eX]

[DOI]

Integr., 2022

Expanding Column Line Code Adaptive (CLC-A) for Protecting 32-and 64-Bit Data.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

Impact of failures in a MPSoC with shared coprocessors to extend the RISC-V ISA.

[BibT_eX]

[DOI]

Jorge Reis

Proceedings of the 11th Latin-American Symposium on Dependable Computing, 2022

Fast Transform Decision Scheme for VVC Intra-Frame Prediction Using Decision Trees.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

Subutai: Speeding Up Legacy Parallel Applications Through Data Synchronization.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2021

LPC: An Error Correction Code for Mitigating Faults in 3D Memories.

[BibT_eX]

[DOI]

David C. C. Freitas

David F. M. Mota

João Cesar M. Mota

IEEE Trans. Computers, 2021

Performance analysis of VVC intra coding.

[BibT_eX]

[DOI]

J. Vis. Commun. Image Represent., 2021

Using curved angular intra-frame prediction to improve video coding efficiency.

[BibT_eX]

[DOI]

J. Vis. Commun. Image Represent., 2021

Fast block partitioning scheme for chrominance intra prediction of versatile video coding standard.

[BibT_eX]

[DOI]

J. Electronic Imaging, 2021

A Trajectory Inference-based Technique for Energy Efficient Store-and-Forward Technology.

[BibT_eX]

[DOI]

Sidnei Renato Silveira

Ricardo Tombesi Macedo

Raul Ceretta Nunes

Proceedings of the 2021 Wireless Days, 2021

Learning-Based Complexity Reduction Scheme for VVC Intra-Frame Prediction.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Visual Communications and Image Processing, 2021

Analysis of VVC Intra Prediction Block Partitioning Structure.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Visual Communications and Image Processing, 2021

Chronos: An Abstract NoC-based Manycore with Preserved Temporal and Spatial Traffic Distribution.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Latin America Symposium on Circuits and System, 2021

LifeSenior - A Health Monitoring IoT System Based on Deep Learning Architecture.

[BibT_eX]

[DOI]

Proceedings of the Human Aspects of IT for the Aged Population. Supporting Everyday Life Activities, 2021

2020

Using Smart Routing for Secure and Dependable NoC-Based MPSoCs.

[BibT_eX]

[DOI]

IEEE/ACM Trans. Netw., 2020

Fast 3D-HEVC Depth Map Encoding Using Machine Learning.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2020

3D-HEVC Bipartition Modes Encoder and Decoder Design Targeting High-Resolution Videos.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Tile Adaptation for Workload Balancing of 3D-HEVC Encoder in Homogeneous Multicore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020

Optimized buffer protection for network-on-chip based on Error Correction Code.

[BibT_eX]

[DOI]

Microelectron. J., 2020

Parallelism exploration for 3D high-efficiency video coding depth modeling mode one.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2020

PCoSA: A product error correction code for use in memory devices targeting space applications.

[BibT_eX]

[DOI]

João Cesar M. Mota

Integr., 2020

Multicore Parallelism Exploration Targeting 3D-HEVC Intra-Frame Prediction.

[BibT_eX]

[DOI]

IEEE Des. Test, 2020

CLC-A: An Adaptive Implementation of the Column Line Code (CLC) ECC.

[BibT_eX]

[DOI]

Proceedings of the 33rd Symposium on Integrated Circuits and Systems Design, 2020

Optimizing RISC-V ISA Usage by Sharing Coprocessors on MPSoC.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin-American Test Symposium, 2020

Error Coverage, Reliability and Cost Analysis of Fault Tolerance Techniques for 32-bit Memories used on Space Missions.

[BibT_eX]

[DOI]

João Cesar M. Mota

Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Open-Source NoC-Based Many-Core for Evaluating Hardware Trojan Detection Methods.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Fast Partitioning Decision Scheme for Versatile Video Coding Intra-Frame Prediction.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Complexity Analysis Of VVC Intra Coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Image Processing, 2020

Fast Intra Mode Decision for 3D-HEVC Depth Map Coding using Decision Trees.

[BibT_eX]

[DOI]

Marcelo Schiavon Porto

Luciano Agostini

Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

2019

Performance Analysis of Depth Intra-Coding in 3D-HEVC.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2019

Analysis of parallel encoding using tiles in 3D High Efficiency Video Coding.

[BibT_eX]

[DOI]

Signal Image Video Process., 2019

Selection of enterprise resource planning software using analytic hierarchy process.

[BibT_eX]

[DOI]

Ricardo M. Czekster

Alessandra H. Jandrey

Enterp. Inf. Syst., 2019

Optimized Fault-Tolerant Buffer Design for Network-on-Chip Applications.

[BibT_eX]

[DOI]

Daniel A. B. Tavares

Felipe G. A. e Silva

Proceedings of the 10th IEEE Latin American Symposium on Circuits & Systems, 2019

TITAN: Tile Timing-Aware Balancing Algorithm for Speeding Up the 3D-HEVC Intra Coding.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018

A reduced computational effort mode-level scheme for 3D-HEVC depth maps intra-frame prediction.

[BibT_eX]

[DOI]

Otávio Alcântara de Lima Jr.

J. Vis. Commun. Image Represent., 2018

An Extensible Code for Correcting Multiple Cell Upset in Memory Arrays.

[BibT_eX]

[DOI]

J. Electron. Test., 2018

Broadcast- and Power-Aware Wireless NoC for Barrier Synchronization in Parallel Computing.

[BibT_eX]

[DOI]

Hemanta Kumar Mondal

Rodrigo Cadore Cataldo

Kevin J. M. Martin

Sujay Deb

Jean-Philippe Diguet

Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Hardware-Oriented Wedgelet Evaluation Skip for DMM-1 in 3D-HEVC.

[BibT_eX]

[DOI]

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

3D-HEVC DMM-1 Parallelism Exploration Targeting Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

Energy saving on DTN using trajectory inference model.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

A path energy control technique for energy efficiency on wireless sensor networks.

[BibT_eX]

[DOI]

F. Tubiello

Leticia Bolzani Poehls

Fabian Vargas

Proceedings of the 9th IEEE Latin American Symposium on Circuits & Systems, 2018

High Efficient Architecture for 3D-HEVC DMM-1 Decoder Targeting 1080p Videos.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

DCDM-Intra: Dynamically Configurable 3D-HEVC Depth Maps Intra-Frame Prediction Algorithm.

[BibT_eX]

[DOI]

Ramon Fernandes

Proceedings of the 2018 IEEE International Conference on Image Processing, 2018

Low Area Reconfigurable Architecture for 3D-HEVC DMMs Decoder Targeting 1080p Videos.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Least-Squares Approximation Surfaces for High Quality Intra-Frame Prediction in Future Video Standards.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Fast 3D-Hevc Depth Maps Intra-Frame Prediction Using Data Mining.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applications.

[BibT_eX]

[DOI]

Jean-Philippe Diguet

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Models of computation for NoC mapping: Timing and energy saving awareness.

[BibT_eX]

[DOI]

Microelectron. J., 2017

Real-time scalable hardware architecture for 3D-HEVC bipartition modes.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2017

An efficient, low-cost ECC approach for critical-application memories.

[BibT_eX]

[DOI]

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

A security-aware routing implementation for dynamic data protection in zone-based MPSoC.

[BibT_eX]

[DOI]

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Low-area scalable hardware architecture for DMM-1 encoder of 3D-HEVC video coding standard.

[BibT_eX]

[DOI]

Filipo Mór

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Latency reduction of fault-tolerant NoCs by employing multiple paths.

[BibT_eX]

[DOI]

Ronaldo T. P. Milfont

Rafael Goncalves Mota

João Marcelo Ferreira

Paulo César Cortez

Daniel A. B. Tavares

Proceedings of the 30th Symposium on Integrated Circuits and Systems Design: Chip on the Sands, 2017

Signal strength as support to mobility detection on failure detectors.

[BibT_eX]

[DOI]

Raul Ceretta Nunes

Proceedings of the Symposium on Applied Computing, 2017

Analysis of routing algorithms generation for irregular NoC topologies.

[BibT_eX]

[DOI]

Ronaldo Milfont

Paulo Cortez

Rafael Mota

Proceedings of the 18th IEEE Latin American Test Symposium, 2017

Evaluation of multiple bit upset tolerant codes for NoCs buffering.

[BibT_eX]

[DOI]

Felipe G. A. e Silva

Walter Magalhaes

Philippe de S. Magalhães

Otávio A. de Lima

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

Complexity reduction by modes reduction in RD-list for intra-frame prediction in 3D-HEVC depth maps.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Edge-aware depth motion estimation - A complexity reduction scheme for 3D-HEVC.

[BibT_eX]

[DOI]

Bruno Zatt

Marcelo Schiavon Porto

Proceedings of the 25th European Signal Processing Conference, 2017

Depth modeling modes complexity control system for the 3D-HEVC video encoder.

[BibT_eX]

[DOI]

Proceedings of the 25th European Signal Processing Conference, 2017

2016

Scenario preprocessing approach for the reconfiguration of fault-tolerant NoC-based MPSoCs.

[BibT_eX]

[DOI]

Giovanni Cordeiro Barroso

Paulo Cortez

Rafael Mota

Microprocess. Microsystems, 2016

DFPS: a fast pattern selector for depth modeling mode 1 in three-dimensional high-efficiency video coding standard.

[BibT_eX]

[DOI]

Lucas Jordani

J. Electronic Imaging, 2016

Energy-aware light-weight DMM-1 patterns decoders with efficiently storage in 3D-HEVC.

[BibT_eX]

[DOI]

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

A security aware routing approach for NoC-based MPSoCs.

[BibT_eX]

[DOI]

Martha Johanna Sepúlveda

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Architectural exploration of Last-Level Caches targeting homogeneous multicore systems.

[BibT_eX]

[DOI]

Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016

Towards risk aware NoCs for data protection in MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2016

DMNI: A specialized network interface for NoC-based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Efficient traffic balancing for NoC routing latency minimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

A dynamic TDMA-based sleep scheduling to minimize WSN energy consumption.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Conference on Networking, Sensing, and Control, 2016

Real-time simplified edge detector architecture for 3D-HEVC depth maps coding.

[BibT_eX]

[DOI]

Marcelo Schiavon Porto

Bruno Zatt

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

3D-HEVC depth maps intra prediction complexity analysis.

[BibT_eX]

[DOI]

Rodrigo Cataldo

Ramon Fernandes

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Efficient routing table minimization for fault-tolerant irregular Network-on-Chip.

[BibT_eX]

[DOI]

Rafael Goncalves Mota

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Software-based mechanism for Network-on-Chip performance increase.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Evaluation of emerging TSV-enabled main memories on the PARSEC benchmark.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

2015

OcNoC: Efficient One-Cycle Router Implementation for 3D Mesh Network-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on VLSI Design, 2015

Smart Reconfiguration Approach for Fault-Tolerant NoC Based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 28th Symposium on Integrated Circuits and Systems Design, 2015

Preprocessing of Scenarios for Fast and Efficient Routing Reconfiguration in Fault-Tolerant NoCs.

[BibT_eX]

[DOI]

Giovanni Cordeiro Barroso

Paulo Cortez

Rafael Mota

Proceedings of the 23rd Euromicro International Conference on Parallel, 2015

Task partitioning optimization algorithm for energy saving and load balance on NoC-based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

A fault prediction module for a fault tolerant NoC operation.

[BibT_eX]

[DOI]

Mathieu Bodin

Omar Andrés Carmona Cortes

Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Differential Evolution on a GPGPU: The Influence of Parameters on Speedup and the Quality of Solutions.

[BibT_eX]

[DOI]

Mônica Sakuray Pais

Filipo Novo Mor

Andrew Rau-Chaplin

Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium Workshop, 2015

A non-intrusive and reconfigurable access control to secure NoCs.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Conference on Electronics, 2015

2014

MoNoC: A monitored network on chip with path adaptation mechanism.

[BibT_eX]

[DOI]

J. Syst. Archit., 2014

Pre-mapping Algorithm for Heterogeneous MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency Minimization.

[BibT_eX]

[DOI]

Proceedings of the 2014 27th International Conference on VLSI Design, 2014

Employing a Timed Colored Petri Net to accomplish an accurate model for Network-on-Chip performance evaluation.

[BibT_eX]

[DOI]

Giovanni Cordeiro Barroso

Paulo César Cortez

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

A monitored NoC with runtime path adaptation.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

The impact of routing arbitration mechanisms on 3D NoC latency.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy.

[BibT_eX]

[DOI]

Proceedings of the 26th Symposium on Integrated Circuits and Systems Design, 2013

An implementation of a distributed fault-tolerant mechanism for 2D mesh NoCs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

A flexible framework for modeling and simulation of multipurpose wireless networks.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Rapid System Prototyping, 2013

Phoenix NoC: A distributed fault tolerant architecture.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012

WSN Experiment and a Grid-Based Network Architecture Proposal.

[BibT_eX]

[DOI]

Fauzi de M. Shubeita

Leonardo A. Amaral

Rubem Dutra Ribeiro Fagundes

Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

Partitioning Algorithms Analysis for Heterogeneous NoC Based MPSoC.

[BibT_eX]

[DOI]

Rubem Dutra Ribeiro Fagundes

Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

Exploiting Modbus Protocol in Wired and Wireless Multilevel Communication Architecture.

[BibT_eX]

[DOI]

Giuliano B. M. Guarese

Proceedings of the 2012 Brazilian Symposium on Computing System Engineering, 2012

Topological impact on latency and throughput: 2D versus 3D NoC comparison.

[BibT_eX]

[DOI]

Rubem Dutra Ribeiro Fagundes

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012

Buffer depth and traffic influence on 3D NoCs performance.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Rapid System Prototyping, 2012

Partitioning and dynamic mapping evaluation for energy consumption minimization on NoC-based MPSoC.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

CAFES: A framework for intrachip application modeling and communication architecture design.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2011

Arbitration and routing impact on NoC design.

[BibT_eX]

[DOI]

Edson I. Moreno

Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Task mapping on NoC-based MPSoCs with faulty tiles: Evaluating the energy consumption and the application execution time.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Rapid System Prototyping, 2011

Partitioning and mapping on NoC-Based MPSoC: an energy consumption saving approach.

[BibT_eX]

[DOI]

Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

Evaluating energy consumption of homogeneous MPSoCs using spare tiles.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

2009

Evaluation of static and dynamic task mapping algorithms in NoC-based MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

2008

Comparison of network-on-chip mapping algorithms targeting low energy consumption.

[BibT_eX]

[DOI]

Edson Ifarraguirre Moreno

IET Comput. Digit. Tech., 2008

High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping.

[BibT_eX]

[DOI]

Sergio Johann Filho

Alexandra Aguiar

Proceedings of the 19th IEEE/IFIP International Symposium on Rapid System Prototyping: RSP 2009, 2008

A Passive 915 MHz UHF RFID Tag.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

A QoS Scheduler for Real-Time Embedded Systems.

[BibT_eX]

[DOI]

David Matschulat

Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

2007

A Flexible Design Flow for a Low Power RFID Tag.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2007, 2007

A VHDL based approach for fast and accurate energy consumption estimations.

[BibT_eX]

[DOI]

Sergio Johann Filho

Proceedings of the IFIP VLSI-SoC 2007, 2007

A 915 MHz UHF low power RFID tag.

[BibT_eX]

[DOI]

Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

ER-EDF: A QoS Scheduler for Real-Time Embedded Systems.

[BibT_eX]

[DOI]

David Matschulat

Proceedings of the 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 2007

High Level RTOS Scheduler Modeling for a Fast Design Validation.

[BibT_eX]

[DOI]

Tatiana Gadelha Serra dos Santos

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Evaluation of Algorithms for Low Energy Mapping onto NoCs.

[BibT_eX]

[DOI]

Edson I. Moreno

Tatiana Gadelha Serra dos Santos

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Scheduling refinement in abstract RTOS models.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2006

RTOS Scheduler Implementation in Hardware and Software for Real Time Applications.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

2005

Modelos para o mapeamento de aplicações em infra-estruturas de comunicação intrachip.

[BibT_eX]

[DOI]

PhD thesis, 2005

Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.

[BibT_eX]

[DOI]

José Carlos S. Palma

Ricardo Augusto da Luz Reis

Proceedings of the VLSI-SoC: From Systems To Silicon, 2005

Mapping embedded systems onto NoCs: the traffic effect on dynamic energy estimation.

[BibT_eX]

[DOI]

José Carlos S. Palma

Ricardo A. L. Reis

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Design space exploration comparing homogeneous and heterogeneous network-on-chip architectures.

[BibT_eX]

[DOI]

Márcio Eduardo Kreutz

Flávio Rech Wagner

Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

Models for Embedded Application Mapping onto NoCs: Timing Analysis.

[BibT_eX]

[DOI]

Márcio Eduardo Kreutz

Proceedings of the 16th IEEE International Workshop on Rapid System Prototyping (RSP 2005), 2005

Energy and latency evaluation of NoC topologies.

[BibT_eX]

[DOI]

Márcio Eduardo Kreutz

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Exploring NoC Mapping Strategies: An Energy and Timing Aware Technique.

[BibT_eX]

[DOI]

Igor M. Reis

Proceedings of the 2005 Design, 2005

Time and energy efficient mapping of embedded applications onto NoCs.

[BibT_eX]

[DOI]

André Borin Suarez

Flávio Rech Wagner

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Abstract RTOS Modeling for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Workshop on Rapid System Prototyping (RSP 2004), 2004

2002

Requirements, Primitives and Models for Systems Specification.

[BibT_eX]

[DOI]

Proceedings of the 15th Annual Symposium on Integrated Circuits and Systems Design, 2002

Prototyping of embedded digital systems from SDL language: a case study.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002

1993

SHC-SLX: A levelized compiled, event driven interpreted VLSI simulator.

[BibT_eX]

[DOI]