Cees-Bart Breunesse

According to our database1, Cees-Bart Breunesse authored at least 9 papers between 2002 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Gate-Level Side-Channel Leakage Ranking With Architecture Correlation Analysis.
IEEE Trans. Emerg. Top. Comput., 2024

Improving CPU Fault Injection Simulations: Insights from RTL to Instruction-Level Models.
Proceedings of the Workshop on Fault Detection and Tolerance in Cryptography, 2024

2023
Special Session: CAD for Hardware Security - Promising Directions for Automation of Security Assurance.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022
Gate-Level Side-Channel Leakage Assessment with Architecture Correlation Analysis.
CoRR, 2022

2021
Rewrite to Reinforce: Rewriting the Binary to Apply Countermeasures against Fault Injection.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Verification of Power-based Side-channel Leakage through Simulation.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2018
Towards Fully Automated Analysis of Whiteboxes: Perfect Dimensionality Reduction for Perfect Leakage.
IACR Cryptol. ePrint Arch., 2018

2005
Formal methods for smart cards: an experience report.
Sci. Comput. Program., 2005

2002
Specifying and Verifying a Decimal Representation in Java for Smart Cards.
Proceedings of the Algebraic Methodology and Software Technology, 2002


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