Cédric Marchand
Orcid: 0000-0002-2546-6662Affiliations:
- University of Lyon, France
According to our database1,
Cédric Marchand
authored at least 26 papers
between 2014 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Complexity Assessment of Analog Security Primitives Using the Disentropy of Autocorrelation.
CoRR, 2024
A Novel Design Technique for Enhanced Security and New Applications of Ferroelectric-Based Non-Volatile SRAM.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis.
Proceedings of the 32nd IFIP/IEEE International Conference on Very Large Scale Integration, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
CoRR, 2023
Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023
Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023
Proceedings of the International Conference on Microelectronics, 2023
EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.
Proceedings of the IEEE European Test Symposium, 2023
2022
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
2021
Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021
2020
3D Logic Cells Design and Results Based on Vertical NWFET Technology Including Tied Compact Model.
Proceedings of the VLSI-SoC: Design Trends, 2020
2018
Implementation and Characterization of a Physical Unclonable Function for IoT: A Case Study With the TERO-PUF.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Prospects for energy-efficient edge computing with integrated HfO2-based ferroelectric devices.
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
2017
Area-oriented comparison of lightweight block ciphers implemented in hardware for the activation mechanism in the anti-counterfeiting schemes.
Int. J. Circuit Theory Appl., 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
2016
Design, Evaluation, and Optimization of Physical Unclonable Functions Based on Transient Effect Ring Oscillators.
IEEE Trans. Inf. Forensics Secur., 2016
Microprocess. Microsystems, 2016
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016
2015
Identification of embedded control units by state encoding and power consumption analysis.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015
2014
Low-level implementation and side-channel detection of stealthy hardware trojans on field programmable gate arrays.
IET Comput. Digit. Tech., 2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014