Cécile Braunstein

According to our database, Cécile Braunstein authored at least 9 papers between 2006 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2014

Complete Model-Based Equivalence Class Testing for the ETCS Ceiling Speed Monitor.

Cécile Braunstein, Anne E. Haxthausen, Wen-ling Huang, Felix Hübner, Jan Peleska, Uwe Schulze, Linh Vu Hong

Proceedings of the Formal Methods and Software Engineering, 2014

2012

Efficient Refinement Strategy Exploiting Component Properties in a CEGAR Process.

Syed Hussein Syed Alwi, Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the Models, Methods, and Tools for Complex Chip Design, 2012

An efficient refinement strategy exploiting component properties in a cegar process.

Syed Hussein Syed Alwi, Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the Proceeding of the 2012 Forum on Specification and Design Languages, 2012

2011

Feasibility analysis for robustness quantification by symbolic model checking.

Souheib Baarir, Cécile Braunstein, Emmanuelle Encrenaz, Jean-Michel Ilié, Isabelle Mounier, Denis Poitrenaud, Sana Younès

Formal Methods Syst. Des., 2011

2009

Increasing the Accuracy of SAT-based Debugging.

André Sülflow, Görschwin Fey, Cécile Braunstein, Ulrich Kühne, Rolf Drechsler

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2009

Complementary Formal Approaches for Dependability Analysis.

Souheib Baarir, Cécile Braunstein, Renaud Clavel, Emmanuelle Encrenaz, Jean-Michel Ilié, Régis Leveugle, Isabelle Mounier, Laurence Pierre, Denis Poitrenaud

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2007

CTL-property Transformations along an Incremental Design Process.

Cécile Braunstein, Emmanuelle Encrenaz

Int. J. Softw. Tools Technol. Transf., 2007

Using CTL formulae as component abstraction in a design and verification flow.

Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006

Formalizing the Incremental Design and Verification Process of a Pipelined Protocol Converter.

Cécile Braunstein, Emmanuelle Encrenaz

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006