Cecil Accetti

According to our database, Cecil Accetti authored at least 8 papers between 2012 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Structured Combinators for Efficient Graph Reduction.

Cecil Accetti, Rendong Ying, Peilin Liu

IEEE Comput. Archit. Lett., 2022

Architectural Support for Functional Programming.

Cecil Accetti, Peilin Liu

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2020

A Platform for Full-Stack Functional Programming.

Cecil Accetti R. de A. Melo, Peilin Liu, Rendong Ying

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018

An FPGA-Based RFID Baseband Processor Using a RISC-V Platform.

Pedro J. A. Ishimaru, Antonyus P. A. Ferreira, Vanessa O. Ogg, Cecil Accetti R. de A. Melo, Edna Natividade da Silva Barros

Proceedings of the 31st Symposium on Integrated Circuits and Systems Design, 2018

A 974GOPS/W Multi-level Parallel Architecture for Binary Weight Network Acceleration.

Rongdi Sun, Peilin Liu, Cecil Accetti, Abid A. Naqvi, Haroon Ahmed, Jiuchao Qian

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017

A 42fps full-HD ORB feature extraction accelerator with reduced memory overhead.

Rongdi Sun, Peilin Liu, Jun Wang, Cecil Accetti, Abid A. Naqvi

Proceedings of the International Conference on Field Programmable Technology, 2017

2016

Oolong: A Baseband processor extension to the RISC-V ISA.

Cecil Accetti R. de A. Melo, Edna Barros

Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2012

FPGA-based digital direct-conversion transceiver for Nuclear Magnetic Resonance Systems.

Cecil Accetti R. de A. Melo, Ricardo E. de Souza

Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012