Cece Huang

According to our database, Cece Huang authored at least 6 papers between 2017 and 2022.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2022

A Residue Amplifier with 85 dB DC Gain and 15 GHz Closed-Loop Bandwidth for 14-Bit 3GSPS Pipeline ADC.

Cece Huang, Weixin Gai, Yuanfu Zhao, Yafei Ji, Fei Chu, Tieliang Zhang

Circuits Syst. Signal Process., 2022

An Input Buffer with 85dB SFDR for High-Speed Pipeline ADC.

Cece Huang, Yuanfu Zhao, Yafei Ji, Xin Yang, Tieliang Zhang, Weixin Gai

Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022

2021

A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories.

Qianqian Wang, Fei Liu, Cece Huang, Qianhui Li, Zongliang Huo

IEEE Trans. Very Large Scale Integr. Syst., 2021

Low Power Program Scheme With Capacitance-Less Charge Recycling for 3D NAND Flash Memory.

Cece Huang, Fei Liu, Qianqian Wang, Zongliang Huo

IEEE Trans. Circuits Syst. II Express Briefs, 2021

2020

A Small Ripple Program Voltage Generator Without High-Voltage Regulator for 3D NAND Flash.

Cece Huang, Fei Liu, Qianqian Wang, Zongliang Huo

IEEE Trans. Circuits Syst. II Express Briefs, 2020

2017

A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology.

Cece Huang, Yu Wang, Teng Chen, Liyin Fu, Qi Wang, Zongliang Huo

IEICE Electron. Express, 2017