Catherine H. Gebotys

Orcid: 0000-0002-7835-3741

Affiliations:
  • University of Waterloo, Canada


According to our database1, Catherine H. Gebotys authored at least 80 papers between 1988 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Bibliography

2021
Quiescent photonics side channel analysis: Low cost SRAM readout attack.
Cryptogr. Commun., 2021

2020
Analysis of Dynamic Laser Injection and Quiescent Photon Emissions on an Embedded Processor.
J. Hardw. Syst. Secur., 2020

EM Fault Injection on ARM and RISC-V.
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020

Going Deep: Using deep learning techniques with simplified mathematical models against XOR BR and TBR PUFs (Attacks and Countermeasures).
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2019
Circumventing Uniqueness of XOR Arbiter PUFs.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Methodology for EM Fault Injection: Charge-based Fault Model.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

PUFs Deep Attacks: Enhanced modeling attacks using deep learning techniques to break the security of double arbiter PUFs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Algebraic Fault Attack on SHA Hash Functions Using Programmatic SAT Solvers.
Proceedings of the Principles and Practice of Constraint Programming, 2018

2017
Adaptive Restart and CEGAR-Based Solver for Inverting Cryptographic Hash Functions.
Proceedings of the Verified Software. Theories, Tools, and Experiments, 2017

A Propagation Rate Based Splitting Heuristic for Divide-and-Conquer Solvers.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2017 - 20th International Conference, Melbourne, VIC, Australia, August 28, 2017

2016
Preaveraging and Carry Propagate Approaches to Side-Channel Analysis of HMAC-SHA256.
ACM Trans. Embed. Comput. Syst., 2016

2015
A Sliding Window Phase-Only Correlation Method for Side-Channel Alignment in a Smartphone.
ACM Trans. Embed. Comput. Syst., 2015

2013
A Quantitative Analysis of a Novel SEU-Resistant SHA-2 and HMAC Architecture for Space Missions Security.
IEEE Trans. Aerosp. Electron. Syst., 2013

Editorial Introduction of New Associate Editors.
IEEE Embed. Syst. Lett., 2013

2011
Counteracting power analysis attack using Static Single-ended Logic.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
SARFUM: Security Architecture for Remote FPGA Update and Monitoring.
ACM Trans. Reconfigurable Technol. Syst., 2010

Analysis of Efficient Techniques for Fast Elliptic Curve Cryptography on x86-64 based Processors.
IACR Cryptol. ePrint Arch., 2010

Efficient Techniques for High-Speed Elliptic Curve Cryptography.
IACR Cryptol. ePrint Arch., 2010

Faster Explicit Formulas for Computing Pairings over Ordinary Curves.
IACR Cryptol. ePrint Arch., 2010

A new correlation frequency analysis of the side channel.
Proceedings of the 5th Workshop on Embedded Systems Security, 2010

2009
Hardware Mechanisms for Memory Authentication: A Survey of Existing Techniques and Engines.
Trans. Comput. Sci., 2009

Fast Multibase Methods and Other Several Optimizations for Elliptic Curve Scalar Multiplication.
IACR Cryptol. ePrint Arch., 2009

Tailoring a Reconfigurable Platform to SHA-256 and HMAC through Custom Instructions and Peripherals.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Efficient Technique for the FPGA Implementation of the AES MixColumns Transformation.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Leakage Power and Side Channel Security of Nanoscale Cryptosystem-on-Chip (CoC).
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Side channel aware leakage management in nanoscale Cryptosystem-on-Chip (CoC).
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008
EM analysis of a wireless Java-based PDA.
ACM Trans. Embed. Comput. Syst., 2008

Novel Precomputation Schemes for Elliptic Curve Cryptosystems.
IACR Cryptol. ePrint Arch., 2008

Setting Speed Records with the (Fractional) Multibase Non-Adjacent Form Method for Efficient Elliptic Curve Scalar Multiplication.
IACR Cryptol. ePrint Arch., 2008

EM alignment using phase for secure embedded systems.
Des. Autom. Embed. Syst., 2008

Forward-Secure Content Distribution to Reconfigurable Hardware.
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

An Approach for Recovering Satellites and their Cryptographic Capabilities in the Presence of SEUs and Attacks.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

2007
Enhanced Current-Balanced Logic (ECBL): An Area Efficient Solution to Secure Smart Cards against Differential Power Attack.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

A Phase Substitution Technique for DEMA of Embedded Cryptographic Systems.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

2006
A table masking countermeasure for low-energy secure embedded systems.
IEEE Trans. Very Large Scale Integr. Syst., 2006

A split-mask countermeasure for low-energy secure embedded systems.
ACM Trans. Embed. Comput. Syst., 2006

Methodology for attack on a Java-based PDA.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

2005
Instantaneous current modeling in a complex VLIW processor core.
ACM Trans. Embed. Comput. Syst., 2005

An Energy-Efficient Image Representation for Secure Mobile Systems.
Proceedings of the NETWORKING 2005: Networking Technologies, 2005

A Countermeasure for EM Attack of a Wireless PDA.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

EM Analysis of Rijndael and ECC on a Wireless Java-Based PDA.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

2004
Design of secure cryptography against the threat of power-attacks in DSP-embedded processors.
ACM Trans. Embed. Comput. Syst., 2004

Current flattening in software and hardware for security applications.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Secure and safety-critical vs. insecure, non safety-critical embedded systems: do they require completely different design approaches?
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Low energy security optimization in embedded cryptographic systems.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003
A Framework for Security on NoC Technologies.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Security wrappers and power analysis for SoC technologies.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
A network flow approach to memory bandwidth utilization in embedded DSP core processors.
IEEE Trans. Very Large Scale Integr. Syst., 2002

Special Session: Security on SoC.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Security-Driven Exploration of Cryptography in DSP Cores.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Secure Elliptic Curve Implementations: An Analysis of Resistance to Power-Attacks in a DSP Processor.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2002

2001
Current consumption dynamics at instruction and program level for a <i>VLIW</i> DSP processor.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Modeling Power Dynamics for an Embedded DSP Processor Core. An Empirical Model.
Proceedings of the SOC Design Methodologies, 2001

Utilizing Memory Bandwidth in DSP Embedded Processors.
Proceedings of the 38th Design Automation Conference, 2001

2000
Power minimization derived from architectural-usage of VLIW processors.
Proceedings of the 37th Conference on Design Automation, 2000

1999
A minimum-cost circulation approach to DSP address-code generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Statistically based prediction of power dissipation for complex embedded DSP processors.
Microprocess. Microsystems, 1999

Designing for Low Power in Complex Embedded DSP Systems.
Proceedings of the 32nd Annual Hawaii International Conference on System Sciences (HICSS-32), 1999

1998
Optimizing Energy During Systems Synthesis of Computer Intensive Realtime Applications.
VLSI Design, 1998

Network Flow Approach to Data Regeneration for Low Energy Embedded System Synthesis.
Integr. Comput. Aided Eng., 1998

An empirical comparison of algorithmic, instruction, and architectural power prediction models for high performance embedded DSP processors.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

Complexities in DSP Software Compilation: Performance, Code Size Power, Retargetability.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1997
Changing Interaction of Compiler and Architecture.
Computer, 1997

An Efficient Model for DSP Code Generation: Performance, Code Size, Estimated Energy.
Proceedings of the 10th International Symposium on System Synthesis, 1997

DSP address optimization using a minimum cost circulation technique.
Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Performance-Power Optimization of Memory Components for Complex Embedded Systems.
Proceedings of the 30th Annual Hawaii International Conference on System Sciences (HICSS-30), 1997

Low Energy Memory and Register Allocation Using Network Flow.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Power Minimization in Heterogeneous Processing.
Proceedings of the 29th Annual Hawaii International Conference on System Sciences (HICSS-29), 1996

1995
An optimal methodology for synthesis of DSP multichip architectures.
J. VLSI Signal Process., 1995

Optimized mapping of video applications to hardware-software for VLSI architectures.
Proceedings of the 28th Annual Hawaii International Conference on System Sciences (HICSS-28), 1995

1994
An optimization approach to the synthesis of multichip architectures.
IEEE Trans. Very Large Scale Integr. Syst., 1994

Application-Specific Architectures for Field-Programmable VLSI Technologies.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993
Throughput optimized architectural synthesis.
IEEE Trans. Very Large Scale Integr. Syst., 1993

Global optimization approach for architectural synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

1992
Optimal synthesis of multichip architectures.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Optimal Scheduling and Allocation of Embedded VLSI Chips.
Proceedings of the 29th Design Automation Conference, 1992

1991
Simultaneous Scheduling and Allocation for Cost Constrained Optimal Architectural Synthesis.
Proceedings of the 28th Design Automation Conference, 1991

1989
Integration of algorithmic VLSI synthesis with testability incorporation.
IEEE J. Solid State Circuits, April, 1989

1988
Integrated design and test synthesis.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

VLSI Design Synthesis with Testability.
Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988


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