Caroline Collange

According to our database1, Caroline Collange authored at least 39 papers between 2006 and 2023.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2023

2020
SIMT-X: Extending Single-Instruction Multi-Threading to Out-of-Order Cores.
ACM Trans. Archit. Code Optim., 2020

2019
Qubit allocation as a combination of subgraph isomorphism and token swapping.
Proc. ACM Program. Lang., 2019

Compressed Cache Layout Aware Prefetching.
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

2018
DITVA: Dynamic Inter-Thread Vectorization Architecture.
J. Parallel Distributed Comput., 2018

Qubit allocation.
Proceedings of the 2018 International Symposium on Code Generation and Optimization, 2018

2017
Function Call Re-Vectorization.
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017

2016
Dynamic Inter-Thread Vectorization Architecture: Extracting DLP from TLP.
Proceedings of the 28th International Symposium on Computer Architecture and High Performance Computing, 2016

Parallel floating-point expansions for extended-precision GPU computations.
Proceedings of the 27th IEEE International Conference on Application-specific Systems, 2016

2015
Numerical reproducibility for the parallel reduction on multi- and many-core architectures.
Parallel Comput., 2015

Fusion of Calling Sites.
Proceedings of the 27th International Symposium on Computer Architecture and High Performance Computing, 2015

Reproducible Triangular Solvers for High-Performance Computing.
Proceedings of the 12th International Conference on Information Technology, 2015

Reproducible floating-point atomic addition in data-parallel environment.
Proceedings of the 2015 Federated Conference on Computer Science and Information Systems, 2015

2014
Options for Denormal Representation in Logarithmic Arithmetic.
J. Signal Process. Syst., 2014

Thread scheduling and memory coalescing for dynamic vectorization of SPMD workloads.
Parallel Comput., 2014

Reproducible and Accurate Matrix Multiplication.
Proceedings of the Scientific Computing, Computer Arithmetic, and Validated Numerics, 2014

2013
Reconvergence de contrôle implicite pour les architectures SIMT.
Tech. Sci. Informatiques, 2013

Divergence analysis.
ACM Trans. Program. Lang. Syst., 2013

The Denormal Logarithmic Number System.
Proceedings of the 24th International Conference on Application-Specific Systems, 2013

2012
Spill Code Placement for SIMD Machines.
Proceedings of the Programming Languages - 16th Brazilian Symposium, 2012

Divergence Analysis with Affine Constraints.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Data and Instruction Uniformity in Minimal Multi-threading.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

Simultaneous branch and warp interweaving for sustained GPU performance.
Proceedings of the 39th International Symposium on Computer Architecture (ISCA 2012), 2012

2011
A Real/Complex Logarithmic Number System ALU.
IEEE Trans. Computers, 2011

2010
Enjeux de conception des architectures GPGPU : unités arithmétiques spécialisées et exploitation de la régularité. (Design challenges of GPGPU architectures: specialized arithmetic units and exploitation of regularity).
PhD thesis, 2010

A Novel Cotransformation for LNS Subtraction.
J. Signal Process. Syst., 2010

Barra: A Parallel Functional Simulator for GPGPU.
Proceedings of the MASCOTS 2010, 2010

Implementing LNS using filtering units of GPUs.
Proceedings of the IEEE International Conference on Acoustics, 2010

2009
Power Consumption of GPUs from a Software Perspective.
Proceedings of the Computational Science, 2009

Using Graphics Processors for Parallelizing Hash-Based Data Carving.
Proceedings of the 42st Hawaii International International Conference on Systems Science (HICSS-42 2009), 2009

Dynamic Detection of Uniform and Affine Vectors in GPGPU Computations.
Proceedings of the Euro-Par 2009, 2009

A Dual-Purpose Real/Complex Logarithmic Number System ALU.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009

2008
État de l'intégration de la virgule flottante dans les processeurs graphiques.
Tech. Sci. Informatiques, 2008

Line-by-line spectroscopic simulations on graphics processing units.
Comput. Phys. Commun., 2008

2007
Monte Carlo Logarithmic Number System for Model Predictive Control.
Proceedings of the FPL 2007, 2007

Cotransformation Provides Area and Accuracy Improvement in an HDL Library for LNS Subtraction.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

LNS Subtraction Using Novel Cotransformation and/or Interpolation.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

Graphic processors to speed-up simulations for the design of high performance solar receptors.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Floating Point or LNS: Choosing the Right Arithmetic on an Aapplication Basis.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006


  Loading...