Carlos Villavieja

Orcid: 0000-0001-6013-6207

According to our database1, Carlos Villavieja authored at least 10 papers between 2011 and 2024.

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Bibliography

2024
Limoncello: Prefetchers for Scale.
Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2024

2023
Towards an Adaptable Systems Architecture for Memory Tiering at Warehouse-Scale.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023

2017
Adaptive Runtime-Assisted Block Prefetching on Chip-Multiprocessors.
Int. J. Parallel Program., 2017

2015
SiNUCA: A Validated Micro-Architecture Simulator.
Proceedings of the 17th IEEE International Conference on High Performance Computing and Communications, 2015

2013
The low power architecture approach towards exascale computing.
J. Comput. Sci., 2013

Energy Efficient Last Level Caches via Last Read/Write Prediction.
Proceedings of the 25th International Symposium on Computer Architecture and High Performance Computing, 2013

2012
On the simulation of large-scale architectures using multiple application abstraction levels.
ACM Trans. Archit. Code Optim., 2012

Energy Savings via Dead Sub-Block Prediction.
Proceedings of the IEEE 24th International Symposium on Computer Architecture and High Performance Computing, 2012

2011
FELI: HW/SW Support for On-Chip Distributed Shared Memory in Multicores.
Proceedings of the Euro-Par 2011 Parallel Processing - 17th International Conference, 2011

DiDi: Mitigating the Performance Impact of TLB Shootdowns Using a Shared TLB Directory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011


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