Carlos Valderrama

Orcid: 0000-0002-1693-6394

Affiliations:
  • University of Mons, Department of Electronics and Microelectronics, Polytechnic Faculty, Belgium


According to our database1, Carlos Valderrama authored at least 38 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Efficient Generalized Electroencephalography-Based Drowsiness Detection Approach with Minimal Electrodes.
Sensors, July, 2024

2023
Discrete Wavelet Transform Coefficients for Drowsiness Detection from EEG Signals.
Proceedings of the 2023 IEEE International Conference on Design, 2023

2022
Automatic Detection of Drowsiness in EEG Records Based on Machine Learning Approaches.
Neural Process. Lett., 2022

2021
A Novel Automate Python Edge-to-Edge: From Automated Generation on Cloud to User Application Deployment on Edge of Deep Neural Networks for Low Power IoT Systems FPGA-Based Acceleration.
Sensors, 2021

User Driven FPGA-Based Design Automated Framework of Deep Neural Networks for Low-Power Low-Cost Edge Computing.
IEEE Access, 2021

Full Python Interface Control: Auto Generation And Adaptation of Deep Neural Networks For Edge Computing and IoT Applications FPGA-Based Acceleration.
Proceedings of the International Conference on INnovations in Intelligent SysTems and Applications, 2021

2020
Proposal of Takagi-Sugeno Fuzzy-PI Controller Hardware.
Sensors, 2020

Low Cost and Low Power Stacked Sparse Autoencoder Hardware Acceleration for Deep Learning Edge Computing Applications.
Proceedings of the 5th International Conference on Advanced Technologies for Signal and Image Processing, 2020

The Perspective of Smart Dust Mesh Based on IoEE for Safety and Security in the Smart Cities.
Proceedings of the Integration of WSN and IoT for Smart Cities, 2020

2019
Variance-Triggered Two-Step GPS Acquisition.
Sensors, 2019

A Survey and Taxonomy of FPGA-based Deep Learning Accelerators.
J. Syst. Archit., 2019

An Edge Computing Robot Experience for Automatic Elderly Mental Health Care Based on Voice.
CoRR, 2019

An Accurate Tool for Modeling, Fingerprinting, Comparison, and Clustering of Parallel Applications Based on Performance Counters.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium Workshops, 2019

Energy-Optimal Configurations for Single-Node HPC Applications.
Proceedings of the 17th International Conference on High Performance Computing & Simulation, 2019

2017
Scalable shared-memory architecture to solve the Knapsack 0/1 problem.
Microprocess. Microsystems, 2017

Adaptive video-based algorithm for accident detection on highways.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

FPGA-based digital tunable wireless transceiver for the TETRA-TETRAPOL bands.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

LP-P<sup>2</sup>IP: A Low-Power Version of P<sup>1</sup>IP Architecture Using Partial Reconfiguration.
Proceedings of the Applied Reconfigurable Computing - 13th International Symposium, 2017

2016
Suitability Analysis of FPGAs for Heterogeneous Platforms in HPC.
IEEE Trans. Parallel Distributed Syst., 2016

Cloud Computing for Enhanced Living Environments.
IEEE Cloud Comput., 2016

FPGA hardware in the loop system for ERTMS-ETCS train equipment testing.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Time-effective GPS time domain signal Acquisition Algorithm.
Proceedings of the International Conference on Localization and GNSS, 2016

2015
P<sup>2</sup>IP: A novel low-latency Programmable Pipeline Image Processor.
Microprocess. Microsystems, 2015

Optimal processor dynamic-energy reduction for parallel workloads on heterogeneous multi-core architectures.
Microprocess. Microsystems, 2015

A hardware architecture for the Branch and Bound Flow-Shop Scheduling algorithm.
Proceedings of the Nordic Circuits and Systems Conference, 2015

2014
A Multi-Resolution FPGA-Based Architecture for Real-Time Edge and Corner Detection.
IEEE Trans. Computers, 2014

Parallel Cyclostationarity-Exploiting Algorithm for Energy-Efficient Spectrum Sensing.
IEICE Trans. Commun., 2014

Dynamic partial reconfiguration manager.
Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Exploring Sequence Alignment Algorithms on FPGA-based Heterogeneous Architectures.
Proceedings of the International Work-Conference on Bioinformatics and Biomedical Engineering, 2014

Hardware Managers with File System Support for Faster Dynamic Partial Reconfiguration.
Proceedings of the IEEE International Symposium on Parallel and Distributed Processing with Applications, 2014

2013
Objective Study of Sensor Relevance for Automatic Cough Detection.
IEEE J. Biomed. Health Informatics, 2013

Accuracy Study of a Real-Time Hybrid Sound Source Localization Algorithm.
Proceedings of the Intelligent Technologies for Interactive Entertainment, 2013

2012
A new self-adapting architecture for feature detection.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

2011
FPGA-based hardware acceleration: A CPU/accelerator interface exploration.
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011

2010
Image and video processing on FPGAs: An exploration framework for real-time applications.
Proceedings of the 10th IFAC Workshop on Programmable Devices and Embedded Systems, 2010

Convergence in reconfigurable embedded systems.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Optimal specification of a receiver blocks from global specifications: Example of IEEE 802.15.4.
Proceedings of the 17th IEEE International Conference on Electronics, 2010

Design of a low latency spectrum analyzer using the Goertzel Algorithm with a Network on Chip.
Proceedings of the 17th IEEE International Conference on Electronics, 2010


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