Carlos Jesús Jiménez-Fernández

Orcid: 0000-0002-5010-337X

According to our database1, Carlos Jesús Jiménez-Fernández authored at least 24 papers between 1995 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Online presence:

On csauthors.net:

Bibliography

2024
TinyJAMBU Hardware Implementation for Low Power.
IEEE Access, 2024


2022
Design and Evaluation of Countermeasures Against Fault Injection Attacks and Power Side-Channel Leakage Exploration for AES Block Cipher.
IEEE Access, 2022

2021
Experimental FIA Methodology Using Clock and Control Signal Modifications under Power Supply and Temperature Variations.
Sensors, 2021

Trivium Stream Cipher Countermeasures Against Fault Injection Attacks and DFA.
IEEE Access, 2021

2020
ASIC Design and Power Characterization of Standard and Low Power Multi-Radix Trivium.
IEEE Trans. Circuits Syst., 2020

Breaking Trivium Stream Cipher Implemented in ASIC Using Experimental Attacks and DFA.
Sensors, 2020

An Academic Approach to FPGA Design Based on a Distance Meter Circuit.
Rev. Iberoam. de Tecnol. del Aprendiz., 2020

Hamming-Code Based Fault Detection Design Methodology for Block Ciphers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

2018
Floorplanning as a practical countermeasure against clock fault attack in Trivium stream cipher.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
Vulnerability Analysis of Trivium FPGA Implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Multiradix Trivium Implementations for Low-Power IoT Hardware.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Power and Energy Issues on Lightweight Cryptography.
J. Low Power Electron., 2017

Trivium hardware implementations for power reduction.
Int. J. Circuit Theory Appl., 2017

2016
Fault attack on FPGA implementations of Trivium stream cipher.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2013
A Programmable and Configurable ASIC to Generate Piecewise-Affine Functions Defined Over General Partitions.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013

2012
Low Power Implementation of Trivium Stream Cipher.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2012

2008
Logic Synthesis.
Proceedings of the Wiley Encyclopedia of Computer Science and Engineering, 2008

2002
Prototyping of Fuzzy Logic-Based Controllers Using Standard FPGA Development Boards.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level.
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Hardware/software codesign methodology for fuzzy controller implementation.
Proceedings of the 2002 IEEE International Conference on Fuzzy Systems, 2002

1998
A design methodology for application specific fuzzy integrated circuits.
Proceedings of the 5th IEEE International Conference on Electronics, Circuits and Systems, 1998

XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers.
Proceedings of the 1998 Design, 1998

1995
VHDL package for description of fuzzy logic controllers.
Proceedings of the Proceedings EURO-DAC'95, 1995


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