Carlos Carreras

Integr., 2019

High-Performance Decoding of Variable-Length Memory Data Packets for FPGA Stream Processing.

[BibT_eX]

[DOI]

Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2018

Automated Timing Characterization of High-Performance Macroblocks for Latency Insensitive FPGA Designs.

[BibT_eX]

[DOI]

Roberto Sierra

Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

2015

A Formal Method for Optimal High-Level Casting of Heterogeneous Fixed-Point Adders and Subtractors.

[BibT_eX]

[DOI]

Roberto Sierra

Carlos A. López Bario

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

2014

Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits.

[BibT_eX]

[DOI]

Bojan Jovanovic

IEEE Trans. Ind. Informatics, 2014

Memory optimization in FPGA-accelerated scientific codes based on unstructured meshes.

[BibT_eX]

[DOI]

J. Syst. Archit., 2014

2012

Evaluation of Rapid Prototyping solutions for a 802.16d frequency Offset estimation Scheme.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2012

A complete dynamic power estimation model for data-paths in FPGA DSP designs.

[BibT_eX]

[DOI]

Integr., 2012

A reduced complexity scheme for carrier frequency synchronization in uplink 802.16e OFDMA.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2012

Turning control flow graphs into function calls: Code generation for heterogeneous architectures.

[BibT_eX]

[DOI]

Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012

2011

Power Measurement Methodology for FPGA Devices.

[BibT_eX]

[DOI]

IEEE Trans. Instrum. Meas., 2011

Mesh traversal and sorting for efficient memory usage in scientific codes.

[BibT_eX]

[DOI]

Pablo Barrio

Proceedings of the 30th IEEE International Performance Computing and Communications Conference, 2011

Power estimation of dividers implemented in FPGAs.

[BibT_eX]

[DOI]

Bojan Jovanovic

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Power Estimation of Embedded Multiplier Blocks in FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Improved schemes for tracking residual frequency offset in DVB-T systems.

[BibT_eX]

[DOI]

IEEE Trans. Consumer Electron., 2010

A Multistandard Frequency Offset Synchronization Scheme for 802.11n, 802.16d, LTE, and DVB-T/H Systems.

[BibT_eX]

[DOI]

Ove Edfors

J. Comput. Networks Commun., 2010

SQNR Estimation of Fixed-Point DSP Algorithms.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2010

Fast fixed-point optimization of DSP algorithms.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Architectural synthesis of DSP circuits under simultaneous error and time constraints.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

SQNR estimation of non-linear fixed-point algorithms.

[BibT_eX]

[DOI]

Proceedings of the 18th European Signal Processing Conference, 2010

Precision-wise architectural synthesis of DSP circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th European Signal Processing Conference, 2010

2009

Architectural Synthesis of Fixed-Point DSP Datapaths Using FPGAs.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2009

Floorplan-based FPGA interconnect power estimation in DSP circuits.

[BibT_eX]

[DOI]

Proceedings of the 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), 2009

A Practical Method for Testing High-Speed Networking Hardware Architectures.

[BibT_eX]

[DOI]

Proceedings of the Fifth International Conference on Networking and Services, 2009

Behavioural Biometrics Hardware Based on Bioinformatics Matching.

[BibT_eX]

[DOI]

Slobodan Bojanic

Vladimir M. Milovanovic

Jelena Popovic

Proceedings of the Computational Intelligence in Security for Information Systems, 2009

2008

Fast and accurate computation of the roundoff noise of linear time-invariant systems.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2008

A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components.

[BibT_eX]

[DOI]

Domenik Helms

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Optimized Architectural Synthesis of Fixed-Point Datapaths.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Analytical High-Level Power Model for LUT-Based Components.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2008

2007

Improved Interval-Based Characterization of Fixed-Point LTI Systems With Feedback Loops.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Fpga Acceleration for DNA Sequence Alignment.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2007

Adding Value to TCP/IP Based Information exchange Security by Specialized Hardware.

[BibT_eX]

[DOI]

Slobodan Bojanic

Proceedings of the First International Conference on Emerging Security Information, 2007

A TCP/IP Fragmentation Monitoring Core For Intrusion Prevention.

[BibT_eX]

Slobodan Bojanic

Proceedings of the 2007 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2007

Switching Activity Models for Power Estimation in FPGA Multipliers.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits.

[BibT_eX]

[DOI]

George A. Constantinides

Peter Y. K. Cheung

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Optimized Synthesis of DSP Cores Combining Logic-based and Embedded FPGA Resources.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

High-Level Synthesis of Multiple Word-Length DSP Algorithms Using Heterogeneous-Resource FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

2005

Extension versus bending for continuum robots.

[BibT_eX]

Proceedings of the ICINCO 2005, 2005

2004

A Generator of High-Speed Floating-Point Modules.

[BibT_eX]

[DOI]

Gerardo Leyva

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Analysis of limit cycles by means of affine arithmetic computer-aided tests.

[BibT_eX]

[DOI]

Proceedings of the 2004 12th European Signal Processing Conference, 2004

Fixed-point refinement of OFDM-based adaptive equalizers: An heuristic approach.

[BibT_eX]

[DOI]

Angel Fernández

Proceedings of the 2004 12th European Signal Processing Conference, 2004

2003

Fast characterization of the noise bounds derived from coefficient and signal quantization.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2001

Interval methods for fault-tree analysis in robotics.

[BibT_eX]

[DOI]

Ian D. Walker

IEEE Trans. Reliab., 2001

2000

On interval methods applied to robot reliability quantification.

[BibT_eX]

[DOI]

Ian D. Walker

Reliab. Eng. Syst. Saf., 2000

Grid-Based Histogram Arithmetic for the Probabilistic Analysis of Functions.

[BibT_eX]

[DOI]

Manuel V. Hermenegildo

Proceedings of the Abstraction, 2000

1999

Bit-Width Selection for Data-Path Implementations.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on System Synthesis, 1999

1996

A Co-Design Methodology Based on Formal Specification and High-level Estimation.

[BibT_eX]

[DOI]

María Luisa López Vallejo

Juan Carlos López

Luis Sánchez

Carlos Delgado Kloos

Natividad Martínez Madrid

Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996

1994

Analytic Model of a Cache Only Memory Architecture.

[BibT_eX]

[DOI]