Carlos Arthur Lang Lisbôa

According to our database1, Carlos Arthur Lang Lisbôa authored at least 28 papers between 2004 and 2016.

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Bibliography

2016
A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility.
J. Signal Process. Syst., 2016

2011
Decimal Hamming: A Software-Implemented Technique to Cope with Soft Errors.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Evaluation of a new low cost software level fault tolerance technique to cope with soft errors.
Proceedings of the 11th Latin American Test Workshop, 2010

A Cost-Effective Technique for Mapping BLUTs to QLUTs in FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Multiple Bit Error Detection and Correction in Memory.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Reliability aware yield improvement technique for nanotechnology based circuits.
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009

Using software invariants for dynamic detection of transient errors.
Proceedings of the 10th Latin American Test Workshop, 2009

Single element correction in sorting algorithms with minimum delay overhead.
Proceedings of the 10th Latin American Test Workshop, 2009

Increasing memory yield in future technologies through innovative design.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Invariant checkers: An efficient low cost technique for run-time transient errors detection.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

A fast error correction technique for matrix multiplication algorithms.
Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

New Challenges for Designers of Fault Tolerant Embedded Systems Based on Future Technologies.
Proceedings of the Analysis, 2009

2008
Hardware and Software Transparency in the Protection of Programs Against SEUs and SETs.
J. Electron. Test., 2008

Majority Logic Mapping for Soft Error Dependability.
J. Electron. Test., 2008

Algorithm Level Fault Tolerance: A Technique to Cope with Long Duration Transient Faults in Matrix Multiplication Algorithms.
Proceedings of the 26th IEEE VLSI Test Symposium (VTS 2008), April 27, 2008

XOR-based Low Cost Checkers for Combinational Logic.
Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

Analyzing the effects of the granularity of recomputation based techniques to cope with radiation induced soft errors.
Proceedings of the 5th Conference on Computing Frontiers, 2008

2007
Using majority logic to cope with long duration transient faults.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A soft error robust and power aware memory design.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Using built-in sensors to cope with long duration transient faults in future technologies.
Proceedings of the 2007 IEEE International Test Conference, 2007

System Level Approaches for Mitigation of Long Duration Transient Faults in Future Technologies.
Proceedings of the 12th European Test Symposium, 2007

A low-SER efficient core processor architecture for future technologies.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Using Memory to Cope with Simultaneous Transient Faults.
Proceedings of the 7th Latin American Test Workshop, 2006

SET Fault Tolerant Combinational Circuits Based on Majority Logic.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Online hardening of programs against SEUs and SETs.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

2005
Going beyond TMR for protection against multiple faults.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005

2004
An Intrinsically Robust Technique for Fault Tolerance under Multiple Upsets.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Arithmetic Operators Robust to Multiple Simultaneous Upsets.
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004


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