Carlos Álvarez

Orcid: 0000-0003-0536-5183

Affiliations:
  • Polytechnic University of Catalonia, Barcelona, Spain
  • Barcelona Supercomputing Center, Spain


According to our database1, Carlos Álvarez authored at least 52 papers between 2001 and 2024.

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Bibliography

2024
Enabling HW-Based Task Scheduling in Large Multicore Architectures.
IEEE Trans. Computers, January, 2024

Automated parallel execution of distributed task graphs with FPGA clusters.
Future Gener. Comput. Syst., 2024


2023
FPGA Framework Improvements for HPC Applications.
Proceedings of the International Conference on Field Programmable Technology, 2023

Accelerating SpMV on FPGAs Through Block-Row Compress: A Task-Based Approach.
Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Improving Performance of HPC Kernels on FPGAs Using High-Level Resource Management.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

b8c: SpMV accelerator implementation leveraging high memory bandwidth.
Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

2022
Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach.
Microprocess. Microsystems, November, 2022

OmpSs@cloudFPGA: An FPGA Task-Based Programming Model with Message Passing.
Proceedings of the 2022 IEEE International Parallel and Distributed Processing Symposium, 2022

Towards Reconfigurable Accelerators in HPC: Designing a Multipurpose eFPGA Tile for Heterogeneous SoCs.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
OmpSs@FPGA Framework for High Performance FPGA Computing.
IEEE Trans. Computers, 2021

The AXIOM Project: IoT on Heterogeneous Embedded Platforms.
IEEE Des. Test, 2021

An FPGA cached sparse matrix vector product (SpMV) for unstructured computational fluid dynamics simulations.
CoRR, 2021


Task-Based Programming Models for Heterogeneous Recurrent Workloads.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2021

2020
Asynchronous runtime with distributed manager for task-based programming models.
Parallel Comput., 2020

Breaking master-slave model between host and FPGAs.
Proceedings of the PPoPP '20: 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2020


2019
A Hardware Runtime for Task-Based Programming Models.
IEEE Trans. Parallel Distributed Syst., 2019

Individual Mobility and Uncertain Geographic Context: Real-time Versus Neighborhood Approximated Exposure to Retail Tobacco Outlets Across the US.
J. Heal. Informatics Res., 2019

LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous Computing.
CoRR, 2019

Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019

2018

Application Acceleration on FPGAs with OmpSs@FPGA.
Proceedings of the International Conference on Field-Programmable Technology, 2018


2017
The AXIOM platform for next-generation cyber physical systems.
Microprocess. Microsystems, 2017

Implementation of the K-Means Algorithm on Heterogeneous Devices: A Use Case Based on an Industrial Dataset.
Proceedings of the Parallel Computing is Everywhere, 2017

General Purpose Task-Dependence Management Hardware for Task-Based Dataflow Programming Models.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

Characterizing and Improving the Performance of Many-Core Task-Based Parallel Programming Runtimes.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Picos, A Hardware Task-Dependence Manager for Task-Based Dataflow Programming Models.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

Exploiting Parallelism on GPUs and FPGAs with OmpSs.
Proceedings of the 1st Workshop on AutotuniNg and aDaptivity AppRoaches for Energy efficient HPC Systems, 2017

2016
MInGLE: An Efficient Framework for Domain Acceleration Using Low-Power Specialized Functional Units.
ACM Trans. Archit. Code Optim., 2016

The AXIOM software layers.
Microprocess. Microsystems, 2016

The Secrets of the Accelerators Unveiled: Tracing Heterogeneous Executions Through OMPT.
Proceedings of the OpenMP: Memory, Devices, and Tasks, 2016

Performance analysis of a hardware accelerator of dependence management for task-based dataflow programming models.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016


2015
Picos: A hardware runtime architecture support for OmpSs.
Future Gener. Comput. Syst., 2015

Coarse-Grain Performance Estimator for Heterogeneous Parallel Computing Architectures like Zynq All-Programmable SoC.
CoRR, 2015

The AXIOM project (Agile, eXtensible, fast I/O Module).
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015


Automatic design of domain-specific instructions for low-power processors.
Proceedings of the 26th IEEE International Conference on Application-specific Systems, 2015

2014
Hybrid Dataflow/von-Neumann Architectures.
IEEE Trans. Parallel Distributed Syst., 2014

OmpSs@Zynq all-programmable SoC ecosystem.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Accelerating an application domain with specialized functional units.
ACM Trans. Archit. Code Optim., 2013

Heterogeneous tasking on SMP/FPGA SoCs: The case of OmpSs and the Zynq.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Analysis of the Task Superscalar Architecture Hardware Design.
Proceedings of the International Conference on Computational Science, 2013

2012
Dynamic Tolerance Region Computing for Multimedia.
IEEE Trans. Computers, 2012

2007
Computación difusa.
PhD thesis, 2007

2005
Fuzzy Memoization for Floating-Point Multimedia Applications.
IEEE Trans. Computers, 2005

2002
Initial Results on Fuzzy Floating Point Computation for Multimedia Processors.
IEEE Comput. Archit. Lett., 2002

Cost effective memory disambiguation for multimedia codes.
Proceedings of the International Conference on Compilers, 2002

2001
On the potential of tolerant region reuse for multimedia applications.
Proceedings of the 15th international conference on Supercomputing, 2001


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