Carlo Samori
Orcid: 0000-0002-7084-0721
According to our database1,
Carlo Samori
authored at least 116 papers
between 1998 and 2024.
Collaborative distances:
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Awards
IEEE Fellow
IEEE Fellow 2017, "For contributions to design of integrated Voltage Controlled Oscillators and Phase-Locked Loops".
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
A 10-GHz Digital-PLL-Based Chirp Generator With Parabolic Non-Uniform Digital Predistortion for FMCW Radars.
IEEE J. Solid State Circuits, December, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Proceedings of the 19th Conference on Ph.D Research in Microelectronics and Electronics, 2024
10.6 A 10GHz FMCW Modulator Achieving 680MHz/μs Chirp Slope and 150kHz rms Frequency Error Based on a Digital-PLL with a Non-Uniform Piecewise-Parabolic Digital Predistortion.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
10.1 An 8.75GHz Fractional-N Digital PLL with a Reverse-Concavity Variable-Slope DTC Achieving 57.3fsrms Integrated Jitter and -252.4dB FoM.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
A 59.3fs Jitter and -62.1dBc Fractional-Spur Digital PLL Based on a Multi-Edge Power-Gating Phase-Detector.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2024
2023
A Low-Spur and Low-Jitter Fractional-N Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
IEEE J. Solid State Circuits, December, 2023
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays.
IEEE J. Solid State Circuits, September, 2023
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.
IEEE J. Solid State Circuits, March, 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
A 76.7fs-lntegrated-Jitter and -71.9dBc In-Band Fractional-Spur Bang-Bang Digital PLL Based on an Inverse-Constant-Slope DTC and FCW Subtractive Dithering.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 9.25GHz Digital PLL with Fractional-Spur Cancellation Based on a Multi-DTC Topology.
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
2022
A 900-MS/s SAR-Based Time-Interleaved ADC With a Fully Programmable Interleaving Factor and On-Chip Scalable Background Calibrations.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
Novel Feed-Forward Technique for Digital Bang-Bang PLL to Achieve Fast Lock and Low Phase Noise.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
IEEE J. Solid State Circuits, 2022
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.
IEEE J. Solid State Circuits, 2022
A 10.2-ENOB, 150-MS/s Redundant SAR ADC With a Quasi-Monotonic Switching Algorithm for Time-Interleaved Converters.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
A 68.6fs<sub>rms</sub>-Total-integrated-Jitter and 1.5µs-LocKing-Time Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 28th IEEE International Conference on Electronics, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
A 3.7-to-4.1GHz Narrowband Digital Bang-Bang PLL with a Multitaps LMS Algorithm to Automatically Control the Bandwidth Achieving 183fs Integrated Jitter.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021
2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.
IEEE J. Solid State Circuits, 2020
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
2019
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power.
IEEE J. Solid State Circuits, 2019
A 30-GHz Digital Sub-Sampling Fractional- $N$ PLL With -238.6-dB Jitter-Power Figure of Merit in 65-nm LP CMOS.
IEEE J. Solid State Circuits, 2019
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Digitally-Intensive Fast Frequency Modulators for FMCW Radars in CMOS : (Invited Paper).
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
2018
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE J. Solid State Circuits, 2018
A 23-GHz Low-Phase-Noise Digital Bang-Bang PLL for Fast Triangular and Sawtooth Chirp Modulation.
IEEE J. Solid State Circuits, 2018
A 23GHz low-phase-noise digital bang-bang PLL for fast triangular and saw-tooth chirp modulation.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
2015
A 1.7 GHz Fractional-N Frequency Synthesizer Based on a Multiplying Delay-Locked Loop.
IEEE J. Solid State Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC).
IEEE J. Solid State Circuits, 2014
An Adaptive Pre-Distortion Technique to Mitigate the DTC Nonlinearity in Digital PLLs.
IEEE J. Solid State Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
21.1 A 1.7GHz MDLL-based fractional-N frequency synthesizer with 1.4ps RMS integrated jitter and 3mW power using a 1b TDC.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2013
Exploiting Stochastic Resonance to Enhance the Performance of Digital Bang-Bang PLLs.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Suppression of Flicker Noise Up-Conversion in a 65-nm CMOS VCO in the 3.0-to-3.6 GHz Band.
IEEE J. Solid State Circuits, 2013
A Wideband Fractional-N PLL With Suppressed Charge-Pump Noise and Automatic Loop Filter Calibration.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Minimum-jitter design of bang-bang PLLs in the presence of 1/f<sup>2</sup> and 1/f<sup>3</sup> DCO noise.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Flicker Noise Up-Conversion due to Harmonic Distortion in Van der Pol CMOS Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
A 20 Mb/s Phase Modulator Based on a 3.6 GHz Digital PLL With -36 dB EVM at 5 mW Power.
IEEE J. Solid State Circuits, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A Wideband 3.6 GHz Digital ΔΣ Fractional-N PLL With Phase Interpolation Divider and Digital Spur Cancellation.
IEEE J. Solid State Circuits, 2011
A 2.9-4.0-GHz Fractional-N Digital PLL With Bang-Bang Phase Detector and 560-fs<sub>rms</sub> Integrated Jitter at 4.5-mW Power.
IEEE J. Solid State Circuits, 2011
A 2.9-to-4.0GHz fractional-N digital PLL with bang-bang phase detector and 560fsrms integrated jitter at 4.5mW power.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Folding of Phase Noise Spectra in Charge-Pump Phase-Locked Loops Induced by Frequency Division.
IEEE Trans. Circuits Syst. II Express Briefs, 2010
EURASIP J. Embed. Syst., 2010
A 3MHz-BW 3.6GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Suppression of flicker noise upconversion in a 65nm CMOS VCO in the 3.0-to-3.6GHz band.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2009
IEEE Trans. Circuits Syst. II Express Briefs, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
Analysis and Characterization of the Effects of Clock Jitter in A/D Converters for Subsampling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE Trans. Circuits Syst. I Regul. Pap., 2006
IEEE J. Solid State Circuits, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE J. Solid State Circuits, 2004
Phase noise and accuracy in quadrature oscillators.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
IEEE Trans. Circuits Syst. II Express Briefs, 2003
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the ESSCIRC 2003, 2003
2002
Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion.
IEEE J. Solid State Circuits, 2002
IEEE J. Solid State Circuits, 2002
IEEE Commun. Mag., 2002
2001
A 2-V 2.5-GHz-104-dBc/Hz at 100 kHz fully integrated VCO with wide-band low-noise automatic amplitude control loop.
IEEE J. Solid State Circuits, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
A -94 dBc/Hz@100 kHz, fully-integrated, 5-GHz, CMOS VCO with 18% tuning range for Bluetooth applications.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IEEE Trans. Instrum. Meas., 2000
IEEE J. Solid State Circuits, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1998
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998