Carlo Galuzzi

Proceedings of the Computing in Cardiology, CinC 2021, Brno, 2021

2019

Discovery of Important Subsequences in Electrocardiogram Beats Using the Nearest Neighbour Algorithm.

[BibT_eX]

[DOI]

CoRR, 2019

2018

A Real-Time Reconfigurable Multichip Architecture for Large-Scale Biophysically Accurate Neuron Simulation.

[BibT_eX]

[DOI]

Jaco Hofmann

Gerrit Jan Christiaanse

IEEE Trans. Biomed. Circuits Syst., 2018

2017

Neuromorphic self-organizing map design for classification of bioelectric-timescale signals.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017

2016

Determining Performance Boundaries on High-Level System Specifications.

[BibT_eX]

[DOI]

Wouter van Teijlingen

Bart Kienhuis

Proceedings of the 19th International Workshop on Software and Compilers for Embedded Systems, 2016

Multi-chip dataflow architecture for massive scale biophysically accurate neuron simulation.

[BibT_eX]

[DOI]

Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

A real-time hybrid neuron network for highly parallel cognitive systems.

[BibT_eX]

[DOI]

Gerrit Jan Christiaanse

Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

2015

Multi-Domain SystemC model of 128-channel time-multiplexed neural interface front-end.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Sequential power per area optimization of multichannel neural recording interface based on dual quadratic programming.

[BibT_eX]

[DOI]

Proceedings of the 7th International IEEE/EMBS Conference on Neural Engineering, 2015

Stochastic noise analysis of neural interface front end.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Low Power Programmable Gain Analog to Digital Converter for Integrated Neural Implant Front End.

[BibT_eX]

[DOI]

Proceedings of the Biomedical Engineering Systems and Technologies, 2015

Noise Analysis of Programmable Gain Analog to Digital Converter for Integrated Neural Implant Front End.

[BibT_eX]

René van Leuken

Proceedings of the BIODEVICES 2015, 2015

2014

Preface.

[BibT_eX]

[DOI]

Alexander V. Veidenbaum

Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014

Towards domain-specific Instruction-Set Generation.

[BibT_eX]

[DOI]

Adithya Pulli

Georgi Gaydadjiev

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

ESL design of customizable real-time neuron networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

2013

Quipu: A Statistical Model for Predicting Hardware Resources.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2013

2012

Evaluation of Runtime Task Mapping Using the rSesame Framework.

[BibT_eX]

[DOI]

Int. J. Reconfigurable Comput., 2012

The Q2 Profiling Framework: Driving Application Mapping for Heterogeneous Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

The Instruction-Set Extension Problem: A Survey.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

High level quantitative hardware prediction modeling using statistical methods.

[BibT_eX]

[DOI]

Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Runtime extraction of memory access information from the application source code.

[BibT_eX]

[DOI]

Marco Corina

Proceedings of the 2011 International Conference on High Performance Computing & Simulation, 2011

2010

Runtime Task Mapping Based on Hardware Configuration Reuse.

[BibT_eX]

[DOI]

Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010

tQUAD - Memory Bandwidth Usage Analysis.

[BibT_eX]

[DOI]

Marco Corina

Proceedings of the 39th International Conference on Parallel Processing, 2010

Evaluation of runtime task mapping heuristics with rSesame - a case study.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

QUAD - A Memory Access Pattern Analyser.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

2009

Automatically fused instructions: algorithms for the customization of the instruction, set of a reconfigurable architecture.

[BibT_eX]

[DOI]

PhD thesis, 2009

High-bandwidth Address Generation Unit.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Introduction to Instruction-Set Customization.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2009

System-level runtime mapping exploration of reconfigurable architectures.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Algorithms for the automatic extension of an instruction-set.

[BibT_eX]

[DOI]

Dimitris Theodoropoulos

Proceedings of the Design, Automation and Test in Europe, 2009

2008

Clustering method for the identification of convex disconnected Multiple Input Multiple Output instructions.

[BibT_eX]

[DOI]

Dimitris Theodoropoulos

Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search.

[BibT_eX]

[DOI]

Dimitris Theodoropoulos

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

A Framework for the Automatic Generation of Instruction-Set Extensions for Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

A Linear Complexity Algorithm for the Generation of Multiple Input Single Output Instructions of Variable Size.

[BibT_eX]

[DOI]

Stamatis Vassiliadis

Proceedings of the Embedded Computer Systems: Architectures, 2007

High-Bandwidth Address Generation Unit.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, 2007

The Spiral Search: A Linear Complexity Algorithm for the Generation of Convex MIMO Instruction-Set Extensions.

[BibT_eX]

[DOI]

Stamatis Vassiliadis

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

A Linear Complexity Algorithm for the Automatic Generation of Convex Multiple Input Multiple Output Instructions.

[BibT_eX]

[DOI]