Carlo Condo
Orcid: 0000-0002-3050-036X
According to our database1,
Carlo Condo
authored at least 74 papers
between 2011 and 2024.
Collaborative distances:
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Bibliography
2024
Special Section on Community Detection in Time-Varying Information and Computing Networks: Theory, Models, and Applications.
IEEE Trans. Emerg. Top. Comput., 2024
2023
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2023
2022
A Fixed Latency ORBGRAND Decoder Architecture With LUT-Aided Error-Pattern Scheduling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Proceedings of the IEEE Globecom 2022 Workshops, 2022
2021
IEEE Commun. Lett., 2021
Proceedings of the 11th International Symposium on Topics in Coding, 2021
Proceedings of the 11th International Symposium on Topics in Coding, 2021
Proceedings of the IEEE International Symposium on Information Theory, 2021
Proceedings of the IEEE Globecom 2021 Workshops, Madrid, Spain, December 7-11, 2021, 2021
2020
IEEE Trans. Signal Process., 2020
High-Throughput Low-Latency Encoder and Decoder for a Class of Generalized Reed-Solomon Codes for Short-Reach Optical Communications.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
IEEE Trans. Computers, 2020
Proceedings of the 2020 IEEE Wireless Communications and Networking Conference, 2020
Proceedings of the Optical Fiber Communications Conference and Exhibition, 2020
Proceedings of the 2020 IEEE International Conference on Communications, 2020
2019
J. Signal Process. Syst., 2019
IEEE Trans. Commun., 2019
IEEE Trans. Circuits Syst. II Express Briefs, 2019
Proceedings of the 2019 IEEE Wireless Communications and Networking Conference, 2019
SC-Flip Decoding of Polar Codes with High Order Error Correction Based on Error Dependency.
Proceedings of the 2019 IEEE Information Theory Workshop, 2019
Proceedings of the IEEE International Symposium on Information Theory, 2019
2018
IEEE Trans. Commun., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 9.52 dB NCG FEC Scheme and 162 b/Cycle Low-Complexity Product Decoder Architecture.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Improved successive cancellation flip decoding of polar codes based on error distribution.
Proceedings of the 2018 IEEE Wireless Communications and Networking Conference Workshops, 2018
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018
Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 IEEE International Conference on Communications, 2018
Proceedings of the IEEE Global Communications Conference, 2018
Memory Management in Successive-Cancellation based Decoders for Multi-Kernel Polar Codes.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
IEEE Trans. Signal Process., 2017
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference Workshops, 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Efficient bit-channel reliability computation for multi-mode polar code encoders and decoders.
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Sparsely-Connected Neural Networks: Towards Efficient VLSI Implementation of Deep Neural Networks.
Proceedings of the 5th International Conference on Learning Representations, 2017
Proceedings of the 2017 IEEE Global Conference on Signal and Information Processing, 2017
On error-correction performance and implementation of polar code list decoders for 5G.
Proceedings of the 55th Annual Allerton Conference on Communication, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 9.96 dB NCG FEC scheme and 164 bits/cycle low-complexity product decoder architecture.
CoRR, 2016
Proceedings of the IEEE International Symposium on Information Theory, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE Global Conference on Signal and Information Processing, 2016
2015
PhD thesis, 2015
Exploiting generalized de-Bruijn/Kautz topologies for flexible iterative channel code decoder architectures.
Integr., 2015
Circuits Syst. Signal Process., 2015
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
IEEE Trans. Aerosp. Electron. Syst., 2014
IEEE Signal Process. Lett., 2014
Energy-efficient multi-standard early stopping criterion for low-density-parity-check iterative decoding.
IET Commun., 2014
A Joint Source/Channel Approach to Strengthen Embedded Programmable Devices against Flash Memory Errors.
IEEE Embed. Syst. Lett., 2014
Rediscovering Logarithmic Diameter Topologies for Low Latency Network-on-Chip-Based Applications.
Proceedings of the 22nd Euromicro International Conference on Parallel, 2014
2013
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
A Joint Communication and Application Simulator for NoC-Based Custom SoCs: LDPC and Turbo Codes Parallel Decoding Case Study.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013
2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
A Flexible LDPC code decoder with a Network on Chip as underlying interconnect architecture
CoRR, 2011
A flexible NoC-based LDPC code decoder implementation and bandwidth reduction methods.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011