Carles Hernández

Orcid: 0000-0001-5393-3195

Affiliations:

Technical University of Valencia (UPV), Spain
Barcelona Supercomputing Center, Spain

According to our database¹, Carles Hernández authored at least 98 papers between 2009 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of three.

Timeline

Legend:

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In proceedings

Article

PhD thesis

Dataset

Other

Bibliography

2025

Exploiting neural networks bit-level redundancy to mitigate the impact of faults at inference.

[BibT_eX]

[DOI]

Izan Catalán

José Flich

Carles Hernández

J. Supercomput., January, 2025

Expanding SafeSU capabilities by leveraging security frameworks for contention monitoring in complex SoCs.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2025

2024

Hardware Acceleration for High-Volume Operations of CRYSTALS-Kyber and CRYSTALS-Dilithium.

[BibT_eX]

[DOI]

Joel Ulises González-Jiménez

Miquel Moretó

ACM Trans. Reconfigurable Technol. Syst., September, 2024

Hashing ATD Tags for Low-Overhead Safe Contention Monitoring.

[BibT_eX]

[DOI]

Pablo Andreu

Pedro López

Carles Hernández

IEEE Comput. Archit. Lett., 2024

A Safety-Critical, RISC-V SoC Integrated and ASIC-Ready Classic McEliece Accelerator.

[BibT_eX]

[DOI]

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2024

2023

Accurately Measuring Contention in Mesh NoCs in Time-Sensitive Embedded Systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2023

A Survey of Recent Developments in Testability, Safety and Security of RISC-V Processors.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypes.

[BibT_eX]

[DOI]

Ilya Tuzov

David de Andrés

Juan-Carlos Ruiz-Garcia

Carles Hernández

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated Chips.

[BibT_eX]

[DOI]

Christelle Charpin-Nicolle

Alejandro Hernán Gloriani

Bernabé Linares-Barranco

Marcel D. van de Burgwal

Geert Van der Plas

Elisa Vianello

Pavel Zaykov

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Achieving Diverse Redundancy for GPU Kernels.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

A Security Model for Randomization-based Protected Caches.

[BibT_eX]

[DOI]

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2022

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform.

[BibT_eX]

[DOI]

CoRR, 2022

Efficient Inference Of Image-Based Neural Network Models In Reconfigurable Systems With Pruning And Quantization.

[BibT_eX]

[DOI]

Proceedings of the 2022 IEEE International Conference on Image Processing, 2022

DVINO: A RISC-V Vector Processor Implemented in 65nm Technology.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design of Circuits and Integrated Systems, 2022

The SELENE Deep Learning Acceleration Framework for Safety-related Applications.

[BibT_eX]

[DOI]

Charles-Alexis Lefebvre

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

SafeSU-2: a Safe Statistics Unit for Space MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices.

[BibT_eX]

[DOI]

IEEE Trans. Sustain. Comput., 2021

Enforcing Predictability of Many-Cores With DCFNoC.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2021

Improving the Robustness of Redundant Execution with Register File Randomization.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

HLS-Based HW/SW Co-Design of the Post-Quantum Classic McEliece Cryptosystem.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

SafeSU: an Extended Statistics Unit for Multicore Timing Interference.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Security, Reliability and Test Aspects of the RISC-V Ecosystem.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

From a FPGA Prototyping Platform to a Computing Platform: The MANGO Experience.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

The RECIPE approach to challenges in deeply heterogeneous high performance systems.

[BibT_eX]

[DOI]

Rafael Tornero Gavilá

Marina Zapater

Microprocess. Microsystems, 2020

HP-DCFNoC: High Performance Distributed Dynamic TDM Scheduler Based on DCFNoC Theory.

[BibT_eX]

[DOI]

IEEE Access, 2020

Distributed Training on a Highly Heterogeneous HPC System.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Software-Only Triple Diverse Redundancy on GPUs for Autonomous Driving Platforms.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual IEEE-IFIP International Conference on Dependable Systems and Networks, 2020

Workshop on High-performance Computing Platforms for Dependable Autonomous Systems.

[BibT_eX]

[DOI]

Carles Hernández

Jaume Abella

Mikel Azkarate-askasua

Roman Obermaisser

Proceedings of the 50th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2020

SELENE: Self-Monitored Dependable Platform for High-Performance Safety-Critical Systems.

[BibT_eX]

[DOI]

Carles Hernández

José Flich

Roberto Paredes

Charles-Alexis Lefebvre

Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020

Software-only based Diverse Redundancy for ASIL-D Automotive Applications on Embedded HPC Platforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

An Academic RISC-V Silicon Implementation Based on Open-Source Components.

[BibT_eX]

[DOI]

Proceedings of the XXXV Conference on Design of Circuits and Integrated Systems, 2020

2019

Locality-aware cache random replacement policies.

[BibT_eX]

[DOI]

J. Syst. Archit., 2019

Time-Randomized Wormhole NoCs for Critical Applications.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2019

Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors.

[BibT_eX]

[DOI]

IEEE Des. Test, 2019

Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2019

Software-only Diverse Redundancy on GPUs for Autonomous Driving Platforms.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior.

[BibT_eX]

[DOI]

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Challenges in Deeply Heterogeneous High Performance Systems.

[BibT_eX]

[DOI]

Rafael Tornero Gavilá

Marina Zapater

Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

High-Integrity GPU Designs for Critical Real-Time Automotive Systems.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on Chip.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Towards limiting the impact of timing anomalies in complex real-time processors.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018

Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262.

[BibT_eX]

[DOI]

Mikel Azkarate-askatsua

Tullio Vardanega

IEEE Trans. Reliab., 2018

EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain.

[BibT_eX]

[DOI]

IEEE Micro, 2018

Reconciling Time Predictability and Performance in Future Computing Systems.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Embedded Computer Systems: Architectures, 2018

RPR: a random replacement policy with limited pathological replacements.

[BibT_eX]

[DOI]

Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems.

[BibT_eX]

[DOI]

Proceedings of the 30th Euromicro Conference on Real-Time Systems, 2018

Design and integration of hierarchical-placement multi-level caches for real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cache side-channel attacks and time-predictability in high-performance critical real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

2017

Adapting TDMA arbitration for measurement-based probabilistic timing analysis.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Modelling bus contention during system early design stages.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study.

[BibT_eX]

[DOI]

Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis.

[BibT_eX]

[DOI]

Proceedings of the Euromicro Conference on Digital System Design, 2017

Design and implementation of a fair credit-based bandwidth sharing scheme for buses.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Probabilistic timing analysis on time-randomized platforms for the space domain.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding.

[BibT_eX]

[DOI]

Proceedings of the Reliable Software Technologies - Ada-Europe 2017, 2017

2016

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2016

Fitting processor architectures for measurement-based probabilistic timing analysis.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2016

Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Resilient random modulo cache memories for probabilistically-analyzable real-time systems.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Modeling RTL fault models behavior to increase the confidence on TSIM-based fault injection.

[BibT_eX]

[DOI]

Jaime Espinosa

Carles Hernández

Jaume Abella

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

PROXIMA: Improving Measurement-Based Timing Analysis through Randomisation and Probabilistic Analysis.

[BibT_eX]

[DOI]

Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016

Improving performance guarantees in wormhole mesh NoC designs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Random modulo: a new processor cache design for real-time critical systems.

[BibT_eX]

[DOI]

Proceedings of the 53rd Annual Design Automation Conference, 2016

2015

Timely Error Detection for Effective Recovery in Light-Lockstep Automotive Systems.

[BibT_eX]

[DOI]

Carles Hernández

Jaume Abella

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Area-efficient snoopy-aware NoC design for high-performance chip multiprocessor systems.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2015

WCET analysis methods: Pitfalls and challenges on their trustworthiness.

[BibT_eX]

[DOI]

Mikel Azkarate-askasua

Jon Pérez

Enrico Mezzetti

Tullio Vardanega

Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015

Characterizing fault propagation in safety-critical processor designs.

[BibT_eX]

[DOI]

Jaime Espinosa

Carles Hernández

Jaume Abella

Proceedings of the 21st IEEE International On-Line Testing Symposium, 2015

CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enabling TDMA Arbitration in the Context of MBPTA.

[BibT_eX]

[DOI]

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis.

[BibT_eX]

[DOI]

Irune Agirre

Mikel Azkarate-askasua

Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Low-cost checkpointing in automotive safety-relevant systems.

[BibT_eX]

[DOI]

Carles Hernández

Jaume Abella

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Analysis and RTL correlation of instruction set simulators for automotive microcontroller robustness verification.

[BibT_eX]

[DOI]

Juan-Carlos Ruiz-Garcia

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Parallel many-core avionics systems.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Embedded Software, 2014

LiVe: Timely Error Detection in Light-Lockstep Safety Critical Systems.

[BibT_eX]

[DOI]

Carles Hernández

Jaume Abella

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

Silicon-aware distributed switch architecture for on-chip networks.

[BibT_eX]

[DOI]

J. Syst. Archit., 2013

2012

On the Impact of Within-Die Process Variation in GALS-Based NoC Performance.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

Enabling High-Performance Crossbars through a Floorplan-Aware Design.

[BibT_eX]

[DOI]

Proceedings of the 41st International Conference on Parallel Processing, 2012

Addressing Link Degradation in NoC-Based ULSI Designs.

[BibT_eX]

[DOI]

Carles Hernández

Federico Silla

José Duato

Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012

2011

Characterizing the impact of process variation on 45 nm NoC-based CMPs.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2011

Self-Calibrating Source Synchronous Communication for Delay Variation Tolerant GALS Network-on-Chip Design.

[BibT_eX]

[DOI]

Int. J. Embed. Real Time Commun. Syst., 2011

Fault-Tolerant Vertical Link Design for Effective 3D Stacking.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2011

A Distributed Switch Architecture for On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Parallel Processing, 2011

Energy and Performance Efficient Thread Mapping in NoC-Based CMPs under Process Variations.

[BibT_eX]

[DOI]

Carles Hernández

Federico Silla

José Duato

Proceedings of the International Conference on Parallel Processing, 2011

2010

Improving the Performance of GALS-Based NoCs in the Presence of Process Variation.

[BibT_eX]

[DOI]

Proceedings of the NOCS 2010, 2010

Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on System on Chip, SoC 2010, Tampere, 2010

A methodology for the characterization of process variation in NoC links.

[BibT_eX]

[DOI]

Carles Hernández

Federico Silla

José Duato

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Yield-oriented evaluation methodology of network-on-chip routing implementations.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A new mechanism to deal with process variability in NoC links.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Carles Hernández

Timeline

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