Carles Ferrer

Orcid: 0000-0002-1475-8790

Affiliations:
  • Autonomous University of Barcelona, Spain
  • Institut de Microelectrònica de Barcelona (CNM-CSIC), Spain


According to our database1, Carles Ferrer authored at least 39 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

Online presence:

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Bibliography

2024
Milliwatt μ-TEG-Powered Vibration Monitoring System for Industrial Predictive Maintenance Applications.
Inf., September, 2024

Model and Implementation of a Novel Heat-Powered Battery-Less IIoT Architecture for Predictive Industrial Maintenance.
Inf., June, 2024

2021
Profiling Attack against RSA Key Generation Based on a Euclidean Algorithm.
Inf., 2021

A novel <i>in vivo</i> 433 MHz radio channel indoor study targeting on power saving for ruminal health monitoring boluses.
Comput. Electron. Agric., 2021

2020
Waste Heat Recovery Unit for Energy Intensive Industries Thermoelectricity Harvesting.
Proceedings of the 29th IEEE International Symposium on Industrial Electronics, 2020

Power electronics for Waste Heat Recovery Unit with MPPT and Without Current Sensing.
Proceedings of the 46th Annual Conference of the IEEE Industrial Electronics Society, 2020

2019
Exploring IIoT and Energy Harvesting Boundaries.
Proceedings of the IECON 2019, 2019

A Self-Powered Wireless Sensor Network.
Proceedings of the Cyber-Physical Systems PhD Workshop 2019, an event held within the CPS Summer School "Designing Cyber-Physical Systems, 2019

2018
A Secure Algorithm for Inversion Modulo 2<sup><i>k</i></sup>.
Cryptogr., 2018

2017
An FPGA-based dynamically reconfigurable platform for emulation of permanent faults in ASICs.
Microelectron. Reliab., 2017

A novel tool-flow for zero-overhead cross-domain error resilient partially reconfigurable X-TMR for SRAM-based FPGAs.
J. Syst. Archit., 2017

2016
Accelerating Particle Filter on FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
AC_ICAP: A Flexible High Speed ICAP Controller.
Int. J. Reconfigurable Comput., 2015

2014
Partial crypto-reconfiguration of nodes based on FPGA for WSN.
Proceedings of the International Carnahan Conference on Security Technology, 2014

2013
A Comparison between Different Error Modeling of MEMS Applied to GPS/INS Integrated Systems.
Sensors, 2013

A system clock precision frequency to code converter for low power supply dependence ROIC.
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

Developing an active balancing model and its Battery Management System platform for lithium ion batteries.
Proceedings of the 22nd IEEE International Symposium on Industrial Electronics, 2013

Particle filters and resampling techniques: Importance in computational complexity analysis.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

Constrained non-linear fitting for stochastic modeling of inertial sensors.
Proceedings of the 2013 Conference on Design and Architectures for Signal and Image Processing, 2013

2012
Design and modeling of a low-power multi-channel integrated circuit for infrared gas recognition.
Microprocess. Microsystems, 2012

Ultra-low temperature dependent ROIC for capacitive sensing platforms.
Proceedings of the 38th Annual Conference on IEEE Industrial Electronics Society, 2012

Analysis and modelling of MEMS inertial measurement unit.
Proceedings of the International Conference on Localization and GNSS, 2012

2011
A 400 mu W Hz-Range Lock-In A/D Frontend Channel for Infrared Spectroscopic Gas Recognition.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Performance-Area Improvement by Partial Reconfiguration for an Aerospace Remote Sensing Application.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011

2010
A 100/μA/Ch fully-integrable lock-in multi-channel frontend for infrared spectroscopic gas recognition.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

HTPCP: GNSS-R multi-channel cross-correlation waveforms post-processing solution for GOLD-RTR instrument.
Proceedings of the 2010 NASA/ESA Conference on Adaptive Hardware and Systems, 2010

2007
Coupled electro-thermal simulation of a DC/DC converter.
Microelectron. Reliab., 2007

Behavioural modelling and simulation for heterogeneous design applied to aerospace inertial microinstrumentation development.
Proceedings of the 2007 Summer Computer Simulation Conference, 2007

2004
Practical Case Example of Inertial MEMS Modeling with VHDL-AMS.
Proceedings of the Forum on specification and Design Languages, 2004

2003
Energy Awareness through Software Optimisation as a Performance Estimate Case Study of the MC68HC908GP32 Microcontroller.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

1998
Overview and capacity of the GPRS (General Packet Radio Service).
Proceedings of the 9th IEEE International Symposium on Personal, 1998

1996
Defect-Oriented vs. Schematic-Level Based Fault Simulation for Mixed-Signal ICs.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Analysis of ISSQ/IDDQ Testing Implementation and Circuit Partitioning in CMOS Cell-Based Design.
Proceedings of the 1996 European Design and Test Conference, 1996

1994
An Approach to the Development of a IDDQ Testable Cell Library.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994

1993
Multi-protocol communications controller.
Microprocess. Microprogramming, 1993

Testability enhancement using physical design rules in a CMOS cell library.
Microprocess. Microprogramming, 1993

Layout-level design for testability rules for a CMOS cell library.
Proceedings of the European Design Automation Conference 1993, 1993

Layout Level Design for Testability Strategy Applied to a CMOS Cell Library.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1990
A new switch-level test pattern generation algorithm based on single path over a graph representation.
Proceedings of the European Design Automation Conference, 1990


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