Carl-Johan H. Seger

According to our database, Carl-Johan H. Seger authored at least 49 papers between 1986 and 2023.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of four.

2023

Bifröst: Creating Hardware With Building Blocks.

Jeremy Pope, Carl-Johan H. Seger

Proceedings of the Forum on Specification & Design Languages, 2023

2021

Formal Verification of Complex Data Paths: An Industrial Experience.

Carl-Johan H. Seger

Proceedings of the Formal Methods - 24th International Symposium, 2021

2020

Stately: An FSM Design Tool.

Jeremy Pope, Jules Saget, Carl-Johan H. Seger

Proceedings of the 18th ACM/IEEE International Conference on Formal Methods and Models for System Design, 2020

Cephalopode: A custom processor aimed at functional language execution for IoT devices.

Jeremy Pope, Jules Saget, Carl-Johan H. Seger

Proceedings of the 18th ACM/IEEE International Conference on Formal Methods and Models for System Design, 2020

2017

Symbolic trajectory evaluation for word-level verification: theory and implementation.

Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry

Formal Methods Syst. Des., 2017

2015

Word-Level Symbolic Trajectory Evaluation.

Supratik Chakraborty, Zurab Khasidashvili, Carl-Johan H. Seger, Rajkumar Gajavelly, Tanmay Haldankar, Dinesh Chhatani, Rakesh Mistry

Proceedings of the Computer Aided Verification - 27th International Conference, 2015

2007

Automatic Abstraction in Symbolic Trajectory Evaluation.

Sara Adams, Magnus Björk, Thomas F. Melham, Carl-Johan H. Seger

Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2005

An industrially effective environment for formal hardware verification.

Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark D. Aagaard, Clark W. Barrett, Don Syme

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

2004

Compositional Specification and Model Checking in GSTE.

Jin Yang, Carl-Johan H. Seger

Proceedings of the Computer Aided Verification, 16th International Conference, 2004

2003

Introduction to generalized symbolic trajectory evaluation.

Jin Yang, Carl-Johan H. Seger

IEEE Trans. Very Large Scale Integr. Syst., 2003

2002

Generalized Symbolic Trajectory Evaluation - Abstraction in Action.

Jin Yang, Carl-Johan H. Seger

Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

2001

Practical Formal Verification in Microprocessor Design.

Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark D. Aagaard, Thomas F. Melham

IEEE Des. Test Comput., 2001

CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination.

John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss

Proceedings of the Computer Aided Verification, 13th International Conference, 2001

2000

Combining functional programming and hardware verification (abstract of invited talk).

Carl-Johan H. Seger

Proceedings of the Fifth ACM SIGPLAN International Conference on Functional Programming (ICFP '00), 2000

A Methodology for Large-Scale Hardware Verification.

Mark D. Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger

Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

Formal verification of iterative algorithms in microprocessors.

Mark D. Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger

Proceedings of the 37th Conference on Design Automation, 2000

Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice.

Carl-Johan H. Seger

Proceedings of the Automated Deduction, 2000

1999

Model Checking Lattices: Using and reasoning about information orders for abstraction.

Scott Hazelhurst, Carl-Johan H. Seger

Log. J. IGPL, 1999

Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving.

Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger

Proceedings of the Theorem Proving in Higher Order Logics, 12th International Conference, 1999

Parametric Representations of Boolean Constraints.

Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger

Proceedings of the 36th Conference on Design Automation, 1999

1998

From lattices to practical formal hardware verification.

Carl-Johan H. Seger

Proceedings of the Programming Concepts and Methods, 1998

Formal Methods in CAD from an Industrial Perspective (abstract).

Carl-Johan H. Seger

Proceedings of the Formal Methods in Computer-Aided Design, 1998

Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment.

Mark D. Aagaard, Robert B. Jones, Carl-Johan H. Seger

Proceedings of the 35th Conference on Design Automation, 1998

1997

Symbolic Trajectory Evaluation.

Scott Hazelhurst, Carl-Johan H. Seger

Proceedings of the Formal Hardware Verification - Methods and Systems in Comparison, 1997

1996

Self-Consistency Checking.

Robert B. Jones, Carl-Johan H. Seger, David L. Dill

Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996

1995

A simple theorem prover based on symbolic trajectory evaluation and BDD's.

Scott Hazelhurst, Carl-Johan H. Seger

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories.

Carl-Johan H. Seger, Randal E. Bryant

Formal Methods Syst. Des., 1995

Automatic Verification of Asynchronous Circuits.

Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger

IEEE Des. Test Comput., 1995

The formal verification of a pipelined double-precision IEEE floating-point multiplier.

Mark D. Aagaard, Carl-Johan H. Seger

Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, 1995

Asynchronous Circuits.

Janusz A. Brzozowski, Carl-Johan H. Seger

Monographs in Computer Science, Springer, ISBN: 978-1-4612-4210-9, 1995

1994

Generalized Ternary Simulation of Sequential Circuits.

Carl-Johan H. Seger, Janusz A. Brzozowski

RAIRO Theor. Informatics Appl., 1994

Digital Circuit Verification Using Partially-Ordered State Models.

Carl-Johan H. Seger, Randal E. Bryant

Proceedings of the 24th IEEE International Symposium on Multiple-Valued Logic, 1994

Automatic Verification of Refinement.

Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger

Proceedings of the Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1994

The Completeness of a Hardware Inference System.

Zheng Zhu, Carl-Johan H. Seger

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

Composing Symbolic Trajectory Evaluation Results.

Scott Hazelhurst, Carl-Johan H. Seger

Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1993

Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment.

Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger

Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993

From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation.

Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger

Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993

The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover.

Jeffrey J. Joyce, Carl-Johan H. Seger

Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993

Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving.

Jeffrey J. Joyce, Carl-Johan H. Seger

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1991

On the Existence of Speed-Independent Circuits.

Carl-Johan H. Seger

Theor. Comput. Sci., 1991

Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation.

Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger

Proceedings of the 28th Design Automation Conference, 1991

A Two-Level Formal Verification Methodology using HOL and COSMOS.

Carl-Johan H. Seger, Jeffrey J. Joyce

Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991

1990

Formal Verification of Digital Circuits Using Symbolic Ternary System Models.

Randal E. Bryant, Carl-Johan H. Seger

Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1989

A unified framework for race analysis of asynchronous networks.

Janusz A. Brzozowski, Carl-Johan H. Seger

J. ACM, 1989

A bounded delay race model.

Carl-Johan H. Seger

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

An Optimistic Ternary Simulation of Gate Races.

Carl-Johan H. Seger, Janusz A. Brzozowski

Theor. Comput. Sci., 1988

1987

A Characterization of Ternary Simulation of Gate Networks.

Janusz A. Brzozowski, Carl-Johan H. Seger

IEEE Trans. Computers, 1987

1986

Robust Storage Structures for Crash Recovery.

David J. Taylor, Carl-Johan H. Seger

IEEE Trans. Computers, 1986

Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary).

Janusz A. Brzozowski, Carl-Johan H. Seger

Proceedings of the Automata, Languages and Programming, 13th International Colloquium, 1986