Câncio Monteiro
Orcid: 0000-0002-5264-2326
According to our database1,
Câncio Monteiro
authored at least 11 papers
between 2011 and 2021.
Collaborative distances:
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Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on orcid.org
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Bibliography
2021
2018
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018
2015
Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design.
IET Circuits Devices Syst., 2015
2014
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
An LSI implementation of a bit-parallel cellular multiplier over GF(2<sup>4</sup>) using secure charge-sharing symmetric adiabatic logic.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level.
Microelectron. J., 2013
Proceedings of the 36th International Conference on Telecommunications and Signal Processing, 2013
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology.
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2011
Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card.
Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011