Can Sitik

According to our database, Can Sitik authored at least 15 papers between 2012 and 2019.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2019

SLECTS: Slew-Driven Clock Tree Synthesis.

Weicheng Liu, Can Sitik, Emre Salman, Baris Taskin, Savithri Sundareswaran, Benjamin Huang

IEEE Trans. Very Large Scale Integr. Syst., 2019

Low Voltage Clock Tree Synthesis with Local Gate Clusters.

Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2016

Design Methodology for Voltage-Scaled Clock Distribution Networks.

Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman

IEEE Trans. Very Large Scale Integr. Syst., 2016

Exploiting useful skew in gated low voltage clock trees.

Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015

FinFET-Based Low-Swing Clocking.

Can Sitik, Emre Salman, Leo Filippini, Sung-Jun Yoon, Baris Taskin

ACM J. Emerg. Technol. Comput. Syst., 2015

Enhanced level shifter for multi-voltage operation.

Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A Novel Static D-Flip-Flop Topology for Low Swing Clocking.

Mallika Rathore, Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Clock Skew Scheduling in the Presence of Heavily Gated Clock Networks.

Weicheng Liu, Emre Salman, Can Sitik, Baris Taskin

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Iterative skew minimization for low swing clocks.

Can Sitik, Baris Taskin

Integr., 2014

High Performance Low Swing Clock Tree Synthesis with Custom D Flip-Flop Design.

Can Sitik, Leo Filippini, Emre Salman, Baris Taskin

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Timing characterization of clock buffers for clock tree synthesis.

Can Sitik, Scott Lerner, Baris Taskin

Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013

A microcontroller-based embedded system design course with PSoC3.

Can Sitik, Prawat Nagvajara, Baris Taskin

Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Multi-corner multi-voltage domain clock mesh design.

Can Sitik, Baris Taskin

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

Skew-bounded low swing clock tree optimization.

Can Sitik, Baris Taskin

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Multi-voltage domain clock mesh design.

Can Sitik, Baris Taskin

Proceedings of the 30th International IEEE Conference on Computer Design, 2012