Camillo Stefanucci

According to our database, Camillo Stefanucci authored at least 11 papers between 2014 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2018

Modeling Surface Recombination with Enhanced Devices Network for Optoelectronics.

Chiara Rossi, Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2017

SPICE modeling of light induced current in silicon with 'Generalized' lumped devices.

Chiara Rossi, Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese

Proceedings of the 47th European Solid-State Device Research Conference, 2017

2016

Methodology for 3-D Substrate Network Extraction for SPICE Simulation of Parasitic Currents in Smart Power ICs.

Pietro Buccella, Camillo Stefanucci, Hao Zou, Yasser Moursy, Ramy Iskander, Jean-Michel Sallese, Maher Kayal

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Active guard ring characterization for Smart Power ICs.

Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese, Maher Kayal

Proceedings of the 2016 MIXDES, 2016

Analysis of substrate currents propagation in HVCMOS technology.

Camillo Stefanucci, Pietro Buccella, Ehrenfried Seebacher, Alexander Steinmair, Maher Kayal, Jean-Michel Sallese

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2015

Modeling parasitic vertical PNP in HVCMOS.

Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Spice simulation of passive protection in smart power ICs.

Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese, Maher Kayal

Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015

Substrate noise modeling with dedicated CAD framework for smart power ICs.

Hao Zou, Yasser Moursy, Ramy Iskander, Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Modeling avalanche breakdown for ESD diodes in integrated circuits.

Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

2014

Optimization strategy of numerical simulations applied to EPFL substrate model.

Camillo Stefanucci, Pietro Buccella, Maher Kayal, Jean-Michel Sallese

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014

Spice simulation of substrate minority carriers propagation with equivalent electrical circuit.

Pietro Buccella, Camillo Stefanucci, Jean-Michel Sallese, Maher Kayal

Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems, 2014