Camille Leroux
Orcid: 0000-0002-7339-9142
According to our database1,
Camille Leroux
authored at least 52 papers
between 2007 and 2025.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2025
SoftwareX, 2025
2024
Computing the Low-Weight codewords of Punctured and Shortened Pre-Transformed polar Codes.
CoRR, 2024
Proceedings of the IEEE Workshop on Signal Processing Systemsm, 2024
2023
Concurr. Comput. Pract. Exp., 2023
Proceedings of the 21st IEEE Interregional NEWCAS Conference, 2023
Proceedings of the 12th International Symposium on Topics in Coding, 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Design and Implementation of a RISC-V core with a Flexible Pipeline for Design Space Exploration.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
2022
Ultra Low Power 32-bit Microcontroller With Minimal Instruction Set for Internet of Things Applications.
Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022
2021
Proceedings of the 11th International Symposium on Topics in Coding, 2021
Proceedings of the 11th International Symposium on Topics in Coding, 2021
2020
Low-Latency Sorter Architecture for Polar Codes Successive-Cancellation-List Decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2020
2019
2018
Ann. des Télécommunications, 2018
MIPP: a Portable C++ SIMD Wrapper and its use for Error Correction Coding in 5G Standard.
Proceedings of the 4th Workshop on Programming Models for SIMD/Vector Processing, 2018
Proceedings of the 10th IEEE International Symposium on Turbo Codes & Iterative Information Processing, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
2017
Memory Requirement Reduction Method for Successive Cancellation Decoding of Polar Codes.
J. Signal Process. Syst., 2017
Proceedings of the 2017 IEEE International Workshop on Signal Processing Systems, 2017
Improving performance of SCMA MPA decoders using estimation of conditional probabilities.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017
2016
IEEE Wirel. Commun. Lett., 2016
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016
Proceedings of the 9th International Symposium on Turbo Codes and Iterative Information Processing, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Conference on Acoustics, 2016
Proceedings of the 24th European Signal Processing Conference, 2016
Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016
2015
An Efficient, Portable and Generic Library for Successive Cancellation Decoding of Polar Codes.
Proceedings of the Languages and Compilers for Parallel Computing, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
2014
High-Throughput Energy-Efficient LDPC Decoders Using Differential Binary Message Passing.
IEEE Trans. Signal Process., 2014
Proceedings of the 2014 IEEE Workshop on Signal Processing Systems, 2014
2013
IEEE Trans. Signal Process., 2013
Partial sums generation architecture for successive cancellation decoding of polar codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013
2012
J. Signal Process. Syst., 2012
Proceedings of the 10th IEEE International NEWCAS Conference, 2012
2011
Turbo Product Code Decoder Without Interleaving Resource: From Parallelism Exploration to High Efficiency Architecture.
J. Signal Process. Syst., 2011
Proceedings of the IEEE International Conference on Acoustics, 2011
2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
2009
High-throughput Block Turbo Decoding: From Full-parallel Architecture to FPGA Prototyping.
J. Signal Process. Syst., 2009
2008
Reed-Solomon Turbo Product Codes for Optical Communications: From Code Optimization to Decoder Design.
EURASIP J. Wirel. Commun. Netw., 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008
2007
Architecture de turbo-décodeur en blocs entièrement parallèle pour la transmission de données au-delà du Gbit/s.
Ann. des Télécommunications, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007